// ****************************************************************************** 
// Copyright     :  Copyright (C) 2021, Hisilicon Technologies Co. Ltd.
// File name     :  aic_sc_reg_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2021/10/23 10:32:49 Create file
// ******************************************************************************

#ifndef __AIC_SC_REG_REG_OFFSET_FIELD_H__
#define __AIC_SC_REG_REG_OFFSET_FIELD_H__

#define AIC_SC_REG_PC_RELOAD_LEN    1
#define AIC_SC_REG_PC_RELOAD_OFFSET 1
#define AIC_SC_REG_PSQ_STOP_LEN     1
#define AIC_SC_REG_PSQ_STOP_OFFSET  0

#define AIC_SC_REG_DBG_CTRL_RESERVED_0_LEN    22
#define AIC_SC_REG_DBG_CTRL_RESERVED_0_OFFSET 10
#define AIC_SC_REG_DBG_RESUME_SC_P_LEN        1
#define AIC_SC_REG_DBG_RESUME_SC_P_OFFSET     9
#define AIC_SC_REG_DBG_RESUME_AIC_P_LEN       1
#define AIC_SC_REG_DBG_RESUME_AIC_P_OFFSET    8
#define AIC_SC_REG_AIV_DBG_OVER_LEN           1
#define AIC_SC_REG_AIV_DBG_OVER_OFFSET        7
#define AIC_SC_REG_CCU_REDIRECT_IFU_LEN       1
#define AIC_SC_REG_CCU_REDIRECT_IFU_OFFSET    6
#define AIC_SC_REG_CCU_STALL_LEN              1
#define AIC_SC_REG_CCU_STALL_OFFSET           1
#define AIC_SC_REG_SINGLE_STEP_LEN            1
#define AIC_SC_REG_SINGLE_STEP_OFFSET         0

#define AIC_SC_REG_DBG_CTRL_RESERVED_1_LEN    28
#define AIC_SC_REG_DBG_CTRL_RESERVED_1_OFFSET 4
#define AIC_SC_REG_VEC_DBG_RESUME_VLD_LEN     1
#define AIC_SC_REG_VEC_DBG_RESUME_VLD_OFFSET  3
#define AIC_SC_REG_VEC_DBG_REG_ROTATE_LEN     1
#define AIC_SC_REG_VEC_DBG_REG_ROTATE_OFFSET  2
#define AIC_SC_REG_VEC_DFX_MODE_EN_LEN        1
#define AIC_SC_REG_VEC_DFX_MODE_EN_OFFSET     1
#define AIC_SC_REG_VEC_DBG_SINGLE_STEP_LEN    1
#define AIC_SC_REG_VEC_DBG_SINGLE_STEP_OFFSET 0

#define AIC_SC_REG_CCU_INIT_DONE_LEN     1
#define AIC_SC_REG_CCU_INIT_DONE_OFFSET  12
#define AIC_SC_REG_CUBE_INIT_DONE_LEN    1
#define AIC_SC_REG_CUBE_INIT_DONE_OFFSET 11
#define AIC_SC_REG_MTE_INIT_DONE_LEN     1
#define AIC_SC_REG_MTE_INIT_DONE_OFFSET  10
#define AIC_SC_REG_UB_INIT_DONE_LEN      1
#define AIC_SC_REG_UB_INIT_DONE_OFFSET   9
#define AIC_SC_REG_RST_DONE_LEN          1
#define AIC_SC_REG_RST_DONE_OFFSET       8
#define AIC_SC_REG_RST_ALL_LEN           1
#define AIC_SC_REG_RST_ALL_OFFSET        0

#define AIC_SC_REG_FAST_PATH_DCACHE_INV_EN_LEN    1
#define AIC_SC_REG_FAST_PATH_DCACHE_INV_EN_OFFSET 3
#define AIC_SC_REG_FAST_PATH_PIPE_RST_EN_LEN      1
#define AIC_SC_REG_FAST_PATH_PIPE_RST_EN_OFFSET   2
#define AIC_SC_REG_FAST_PATH_ICACHE_INV_EN_LEN    1
#define AIC_SC_REG_FAST_PATH_ICACHE_INV_EN_OFFSET 1
#define AIC_SC_REG_FAST_PATH_EN_LEN               1
#define AIC_SC_REG_FAST_PATH_EN_OFFSET            0

#define AIC_SC_REG_EXCEPT_INT_LEN               1
#define AIC_SC_REG_EXCEPT_INT_OFFSET            9
#define AIC_SC_REG_TRAP_INT_LEN                 1
#define AIC_SC_REG_TRAP_INT_OFFSET              8
#define AIC_SC_REG_BLK_WARN_DONE_INT_LEN        1
#define AIC_SC_REG_BLK_WARN_DONE_INT_OFFSET     7
#define AIC_SC_REG_WARN_AS_EXCEPTION_INT_LEN    1
#define AIC_SC_REG_WARN_AS_EXCEPTION_INT_OFFSET 6
#define AIC_SC_REG_HW_BKPT_INT_LEN              1
#define AIC_SC_REG_HW_BKPT_INT_OFFSET           5
#define AIC_SC_REG_CCU_STALL_INT_LEN            1
#define AIC_SC_REG_CCU_STALL_INT_OFFSET         4
#define AIC_SC_REG_SINGLE_STEP_INT_LEN          1
#define AIC_SC_REG_SINGLE_STEP_INT_OFFSET       3
#define AIC_SC_REG_CCU_TIMEOUT_INT_LEN          1
#define AIC_SC_REG_CCU_TIMEOUT_INT_OFFSET       2
#define AIC_SC_REG_SW_BKPT_INT_LEN              1
#define AIC_SC_REG_SW_BKPT_INT_OFFSET           1
#define AIC_SC_REG_BLK_NORM_INT_LEN             1
#define AIC_SC_REG_BLK_NORM_INT_OFFSET          0

#define AIC_SC_REG_TRAP_INT_MASK_LEN                 1
#define AIC_SC_REG_TRAP_INT_MASK_OFFSET              8
#define AIC_SC_REG_BLK_WARN_DONE_INT_MASK_LEN        1
#define AIC_SC_REG_BLK_WARN_DONE_INT_MASK_OFFSET     7
#define AIC_SC_REG_WARN_AS_EXCEPTION_INT_MASK_LEN    1
#define AIC_SC_REG_WARN_AS_EXCEPTION_INT_MASK_OFFSET 6
#define AIC_SC_REG_HW_BKPT_INT_MASK_LEN              1
#define AIC_SC_REG_HW_BKPT_INT_MASK_OFFSET           5
#define AIC_SC_REG_CCU_STALL_INT_MASK_LEN            1
#define AIC_SC_REG_CCU_STALL_INT_MASK_OFFSET         4
#define AIC_SC_REG_SINGLE_STEP_INT_MASK_LEN          1
#define AIC_SC_REG_SINGLE_STEP_INT_MASK_OFFSET       3
#define AIC_SC_REG_CCU_TIMEOUT_INT_MASK_LEN          1
#define AIC_SC_REG_CCU_TIMEOUT_INT_MASK_OFFSET       2
#define AIC_SC_REG_SW_BKPT_INT_MASK_LEN              1
#define AIC_SC_REG_SW_BKPT_INT_MASK_OFFSET           1
#define AIC_SC_REG_BLK_NORM_INT_MASK_LEN             1
#define AIC_SC_REG_BLK_NORM_INT_MASK_OFFSET          0

#define AIC_SC_REG_RST_DONE_CNT_LEN    8
#define AIC_SC_REG_RST_DONE_CNT_OFFSET 8
#define AIC_SC_REG_RST_CNT_LEN         8
#define AIC_SC_REG_RST_CNT_OFFSET      0

#define AIC_SC_REG_MTE_AIPP_ECC_EN_N_LEN    1
#define AIC_SC_REG_MTE_AIPP_ECC_EN_N_OFFSET 18
#define AIC_SC_REG_MTE_ROB_ECC_EN_N_LEN     1
#define AIC_SC_REG_MTE_ROB_ECC_EN_N_OFFSET  17
#define AIC_SC_REG_MTE_STB_ECC_EN_N_LEN     1
#define AIC_SC_REG_MTE_STB_ECC_EN_N_OFFSET  16
#define AIC_SC_REG_CCU_ECC_WB_EN_N_LEN      1
#define AIC_SC_REG_CCU_ECC_WB_EN_N_OFFSET   15
#define AIC_SC_REG_CCU_ECC_EN_N_LEN         1
#define AIC_SC_REG_CCU_ECC_EN_N_OFFSET      14
#define AIC_SC_REG_TLU_ECC_WB_EN_N_LEN      1
#define AIC_SC_REG_TLU_ECC_WB_EN_N_OFFSET   13
#define AIC_SC_REG_UB_ECC_WB_EN_N_LEN       1
#define AIC_SC_REG_UB_ECC_WB_EN_N_OFFSET    12
#define AIC_SC_REG_L0C_ECC_WB_EN_N_LEN      1
#define AIC_SC_REG_L0C_ECC_WB_EN_N_OFFSET   11
#define AIC_SC_REG_L0B_ECC_WB_EN_N_LEN      1
#define AIC_SC_REG_L0B_ECC_WB_EN_N_OFFSET   10
#define AIC_SC_REG_L0A_ECC_WB_EN_N_LEN      1
#define AIC_SC_REG_L0A_ECC_WB_EN_N_OFFSET   9
#define AIC_SC_REG_L1_ECC_WB_EN_N_LEN       1
#define AIC_SC_REG_L1_ECC_WB_EN_N_OFFSET    8
#define AIC_SC_REG_TLU_ECC_EN_N_LEN         1
#define AIC_SC_REG_TLU_ECC_EN_N_OFFSET      5
#define AIC_SC_REG_UB_ECC_EN_N_LEN          1
#define AIC_SC_REG_UB_ECC_EN_N_OFFSET       4
#define AIC_SC_REG_L0C_ECC_EN_N_LEN         1
#define AIC_SC_REG_L0C_ECC_EN_N_OFFSET      3
#define AIC_SC_REG_L0B_ECC_EN_N_LEN         1
#define AIC_SC_REG_L0B_ECC_EN_N_OFFSET      2
#define AIC_SC_REG_L0A_ECC_EN_N_LEN         1
#define AIC_SC_REG_L0A_ECC_EN_N_OFFSET      1
#define AIC_SC_REG_L1_ECC_EN_N_LEN          1
#define AIC_SC_REG_L1_ECC_EN_N_OFFSET       0

#define AIC_SC_REG_BUS_AXI_RST_ACK_3_LEN     1
#define AIC_SC_REG_BUS_AXI_RST_ACK_3_OFFSET  6
#define AIC_SC_REG_BUS_AXI_RST_ACK_2_LEN     1
#define AIC_SC_REG_BUS_AXI_RST_ACK_2_OFFSET  5
#define AIC_SC_REG_BUS_AXI_RST_BYPASS_LEN    1
#define AIC_SC_REG_BUS_AXI_RST_BYPASS_OFFSET 4
#define AIC_SC_REG_BUS_AXI_RST_ACK_1_LEN     1
#define AIC_SC_REG_BUS_AXI_RST_ACK_1_OFFSET  3
#define AIC_SC_REG_BUS_AXI_RST_REQ_LEN       1
#define AIC_SC_REG_BUS_AXI_RST_REQ_OFFSET    2
#define AIC_SC_REG_CFG_FORCE_REQ_ACK_LEN     1
#define AIC_SC_REG_CFG_FORCE_REQ_ACK_OFFSET  1
#define AIC_SC_REG_BUS_AXI_RST_ACK_LEN       1
#define AIC_SC_REG_BUS_AXI_RST_ACK_OFFSET    0

#define AIC_SC_REG_AXI_SOFTRST_STATE0_LEN    32
#define AIC_SC_REG_AXI_SOFTRST_STATE0_OFFSET 0

#define AIC_SC_REG_AXI_SOFTRST_STATE1_LEN    32
#define AIC_SC_REG_AXI_SOFTRST_STATE1_OFFSET 0

#define AIC_SC_REG_CLK_CUBE_BIASBUF_EN_MASK_LEN         1
#define AIC_SC_REG_CLK_CUBE_BIASBUF_EN_MASK_OFFSET      28
#define AIC_SC_REG_CLK_FIXP_SUB_EN_MASK_LEN             1
#define AIC_SC_REG_CLK_FIXP_SUB_EN_MASK_OFFSET          27
#define AIC_SC_REG_CLK_CCU_DC_EN_MASK_LEN               1
#define AIC_SC_REG_CLK_CCU_DC_EN_MASK_OFFSET            26
#define AIC_SC_REG_CLK_CCU_SBUF_EN_MASK_LEN             1
#define AIC_SC_REG_CLK_CCU_SBUF_EN_MASK_OFFSET          25
#define AIC_SC_REG_CLK_CUBE_FIFO_EN_MASK_LEN            1
#define AIC_SC_REG_CLK_CUBE_FIFO_EN_MASK_OFFSET         24
#define AIC_SC_REG_CLK_MTE_SMASK_EN_MASK_LEN            1
#define AIC_SC_REG_CLK_MTE_SMASK_EN_MASK_OFFSET         23
#define AIC_SC_REG_CLK_VEC_VALU_DIV_EN_MASK_LEN         1
#define AIC_SC_REG_CLK_VEC_VALU_DIV_EN_MASK_OFFSET      22
#define AIC_SC_REG_REG_CLK_SEL_LEN                      1
#define AIC_SC_REG_REG_CLK_SEL_OFFSET                   21
#define AIC_SC_REG_CLK_MTE_AIPP_SCALER_EN_MASK_LEN      2
#define AIC_SC_REG_CLK_MTE_AIPP_SCALER_EN_MASK_OFFSET   19
#define AIC_SC_REG_CLK_VEC_VALU_RPN_EN_MASK_LEN         1
#define AIC_SC_REG_CLK_VEC_VALU_RPN_EN_MASK_OFFSET      18
#define AIC_SC_REG_CLK_VEC_VALU_MAU_EN_MASK_LEN         1
#define AIC_SC_REG_CLK_VEC_VALU_MAU_EN_MASK_OFFSET      17
#define AIC_SC_REG_CLK_VEC_VALU_LUT_EN_MASK_LEN         1
#define AIC_SC_REG_CLK_VEC_VALU_LUT_EN_MASK_OFFSET      16
#define AIC_SC_REG_CLK_VEC_VALU_IMUX_EN_MASK_LEN        1
#define AIC_SC_REG_CLK_VEC_VALU_IMUX_EN_MASK_OFFSET     15
#define AIC_SC_REG_CLK_VEC_VALU_GRP_EN_MASK_LEN         1
#define AIC_SC_REG_CLK_VEC_VALU_GRP_EN_MASK_OFFSET      14
#define AIC_SC_REG_CLK_VEC_VALU_CMP_CONV_EN_MASK_LEN    1
#define AIC_SC_REG_CLK_VEC_VALU_CMP_CONV_EN_MASK_OFFSET 13
#define AIC_SC_REG_CLK_VEC_VDP_EN_MASK_LEN              1
#define AIC_SC_REG_CLK_VEC_VDP_EN_MASK_OFFSET           12
#define AIC_SC_REG_CLK_MTE_SUB_EN_MASK_LEN              1
#define AIC_SC_REG_CLK_MTE_SUB_EN_MASK_OFFSET           11
#define AIC_SC_REG_CLK_CCU_UB_EN_MASK_LEN               1
#define AIC_SC_REG_CLK_CCU_UB_EN_MASK_OFFSET            10
#define AIC_SC_REG_CLK_IFU_EN_MASK_LEN                  1
#define AIC_SC_REG_CLK_IFU_EN_MASK_OFFSET               9
#define AIC_SC_REG_CLK_IB_EN_MASK_LEN                   1
#define AIC_SC_REG_CLK_IB_EN_MASK_OFFSET                8
#define AIC_SC_REG_CLK_CUBE_PE_EN_MASK_LEN              1
#define AIC_SC_REG_CLK_CUBE_PE_EN_MASK_OFFSET           7
#define AIC_SC_REG_CLK_CCU_VEC_EN_MASK_LEN              1
#define AIC_SC_REG_CLK_CCU_VEC_EN_MASK_OFFSET           6
#define AIC_SC_REG_CLK_CCU_MTE_EN_MASK_LEN              1
#define AIC_SC_REG_CLK_CCU_MTE_EN_MASK_OFFSET           5
#define AIC_SC_REG_CLK_CUBE_L0C_EN_MASK_LEN             1
#define AIC_SC_REG_CLK_CUBE_L0C_EN_MASK_OFFSET          4
#define AIC_SC_REG_CLK_CUBE_L0B_EN_MASK_LEN             1
#define AIC_SC_REG_CLK_CUBE_L0B_EN_MASK_OFFSET          3
#define AIC_SC_REG_CLK_CUBE_L0A_EN_MASK_LEN             1
#define AIC_SC_REG_CLK_CUBE_L0A_EN_MASK_OFFSET          2
#define AIC_SC_REG_CLK_CCU_EX_EN_MASK_LEN               1
#define AIC_SC_REG_CLK_CCU_EX_EN_MASK_OFFSET            1
#define AIC_SC_REG_CLK_CCU_CUBE_EN_MASK_LEN             1
#define AIC_SC_REG_CLK_CCU_CUBE_EN_MASK_OFFSET          0

#define AIC_SC_REG_CLK_GLOBAL_EN_MASK_LEN                   1
#define AIC_SC_REG_CLK_GLOBAL_EN_MASK_OFFSET                31
#define AIC_SC_REG_DEBUG_MODE_EN_LEN                        1
#define AIC_SC_REG_DEBUG_MODE_EN_OFFSET                     30
#define AIC_SC_REG_CLK_CUBE_L0B_OFFSET_TABLE_EN_MASK_LEN    1
#define AIC_SC_REG_CLK_CUBE_L0B_OFFSET_TABLE_EN_MASK_OFFSET 27
#define AIC_SC_REG_CLK_VEC_EN_MASK_LEN                      25
#define AIC_SC_REG_CLK_VEC_EN_MASK_OFFSET                   2
#define AIC_SC_REG_CLK_SU_IQ_EN_MASK_LEN                    1
#define AIC_SC_REG_CLK_SU_IQ_EN_MASK_OFFSET                 1
#define AIC_SC_REG_CLK_SU_FIXP_EN_MASK_LEN                  1
#define AIC_SC_REG_CLK_SU_FIXP_EN_MASK_OFFSET               0

#define AIC_SC_REG_CLK_CCU_UB_DELAY_CNT_LEN      5
#define AIC_SC_REG_CLK_CCU_UB_DELAY_CNT_OFFSET   24
#define AIC_SC_REG_CLK_CCU_CUBE_DELAY_CNT_LEN    5
#define AIC_SC_REG_CLK_CCU_CUBE_DELAY_CNT_OFFSET 16
#define AIC_SC_REG_CLK_CCU_MTE_DELAY_CNT_LEN     5
#define AIC_SC_REG_CLK_CCU_MTE_DELAY_CNT_OFFSET  8
#define AIC_SC_REG_CLK_CCU_VEC_DELAY_CNT_LEN     5
#define AIC_SC_REG_CLK_CCU_VEC_DELAY_CNT_OFFSET  0

#define AIC_SC_REG_SC_CLK_TOP_OFF_DLY_CNT_LEN    8
#define AIC_SC_REG_SC_CLK_TOP_OFF_DLY_CNT_OFFSET 16
#define AIC_SC_REG_SC_CLK_ALL_OFF_DLY_CNT_LEN    8
#define AIC_SC_REG_SC_CLK_ALL_OFF_DLY_CNT_OFFSET 0

#define AIC_SC_REG_ICG_EN_MBIST_LEN             1
#define AIC_SC_REG_ICG_EN_MBIST_OFFSET          9
#define AIC_SC_REG_ICG_EN_SMMU_TRANS_LEN        1
#define AIC_SC_REG_ICG_EN_SMMU_TRANS_OFFSET     8
#define AIC_SC_REG_MBIST2UB16MEM_ALL_SEL_LEN    6
#define AIC_SC_REG_MBIST2UB16MEM_ALL_SEL_OFFSET 0

#define AIC_SC_REG_AXI_SOFTRST_STATE0_1_LEN    32
#define AIC_SC_REG_AXI_SOFTRST_STATE0_1_OFFSET 0

#define AIC_SC_REG_AXI_SOFTRST_STATE1_1_LEN    32
#define AIC_SC_REG_AXI_SOFTRST_STATE1_1_OFFSET 0

#define AIC_SC_REG_LOCK_BYPASS0_EN_LEN         1
#define AIC_SC_REG_LOCK_BYPASS0_EN_OFFSET      31
#define AIC_SC_REG_LOCK_BYPASS0_MASK_N_LEN     15
#define AIC_SC_REG_LOCK_BYPASS0_MASK_N_OFFSET  16
#define AIC_SC_REG_LOCK_BYPASS0_SRCID_L_LEN    9
#define AIC_SC_REG_LOCK_BYPASS0_SRCID_L_OFFSET 7
#define AIC_SC_REG_LOCK_BYPASS0_LPID_LEN       3
#define AIC_SC_REG_LOCK_BYPASS0_LPID_OFFSET    4
#define AIC_SC_REG_LOCK_BYPASS0_SRCID_H_LEN    3
#define AIC_SC_REG_LOCK_BYPASS0_SRCID_H_OFFSET 1

#define AIC_SC_REG_LOCK_BYPASS1_EN_LEN         1
#define AIC_SC_REG_LOCK_BYPASS1_EN_OFFSET      31
#define AIC_SC_REG_LOCK_BYPASS1_MASK_N_LEN     15
#define AIC_SC_REG_LOCK_BYPASS1_MASK_N_OFFSET  16
#define AIC_SC_REG_LOCK_BYPASS1_SRCID_L_LEN    9
#define AIC_SC_REG_LOCK_BYPASS1_SRCID_L_OFFSET 7
#define AIC_SC_REG_LOCK_BYPASS1_LPID_LEN       3
#define AIC_SC_REG_LOCK_BYPASS1_LPID_OFFSET    4
#define AIC_SC_REG_LOCK_BYPASS1_SRCID_H_LEN    3
#define AIC_SC_REG_LOCK_BYPASS1_SRCID_H_OFFSET 1

#define AIC_SC_REG_SYSCTRL_LOCK_LEN    32
#define AIC_SC_REG_SYSCTRL_LOCK_OFFSET 0

#define AIC_SC_REG_VA_0_LEN    30
#define AIC_SC_REG_VA_0_OFFSET 2

#define AIC_SC_REG_IFU_PRELOAD_CNT_LEN    5
#define AIC_SC_REG_IFU_PRELOAD_CNT_OFFSET 27
#define AIC_SC_REG_VA_1_LEN               16
#define AIC_SC_REG_VA_1_OFFSET            0

#define AIC_SC_REG_PARA_BASE_0_LEN    32
#define AIC_SC_REG_PARA_BASE_0_OFFSET 0

#define AIC_SC_REG_PARA_BASE_1_LEN    32
#define AIC_SC_REG_PARA_BASE_1_OFFSET 0

#define AIC_SC_REG_TWO_LEVEL_SMMU_STREAMID_LEN    16
#define AIC_SC_REG_TWO_LEVEL_SMMU_STREAMID_OFFSET 16
#define AIC_SC_REG_SMMU_SUBSTREAMID_LEN           16
#define AIC_SC_REG_SMMU_SUBSTREAMID_OFFSET        0

#define AIC_SC_REG_TWO_LEVEL_EN_LEN    1
#define AIC_SC_REG_TWO_LEVEL_EN_OFFSET 0

#define AIC_SC_REG_PMU_FIFO_PUSH_EN_LEN            1
#define AIC_SC_REG_PMU_FIFO_PUSH_EN_OFFSET         31
#define AIC_SC_REG_WARN_STATUS_FIFO_PUSH_EN_LEN    1
#define AIC_SC_REG_WARN_STATUS_FIFO_PUSH_EN_OFFSET 30
#define AIC_SC_REG_SPR_STATUS_FIFO_PUSH_EN_LEN     1
#define AIC_SC_REG_SPR_STATUS_FIFO_PUSH_EN_OFFSET  29
#define AIC_SC_REG_MIX_MODE_TASK_EN_LEN            1
#define AIC_SC_REG_MIX_MODE_TASK_EN_OFFSET         28
#define AIC_SC_REG_TASK_ID_LEN                     6
#define AIC_SC_REG_TASK_ID_OFFSET                  16
#define AIC_SC_REG_BLOCK_ID_LEN                    16
#define AIC_SC_REG_BLOCK_ID_OFFSET                 0

#define AIC_SC_REG_PIPE_RST_BEFORE_STARTUP_LEN      1
#define AIC_SC_REG_PIPE_RST_BEFORE_STARTUP_OFFSET   31
#define AIC_SC_REG_ICACHE_INV_BEFORE_STARTUP_LEN    1
#define AIC_SC_REG_ICACHE_INV_BEFORE_STARTUP_OFFSET 30
#define AIC_SC_REG_BIU_INSTR_LEN                    1
#define AIC_SC_REG_BIU_INSTR_OFFSET                 29
#define AIC_SC_REG_BIU_NON_SECURE_LEN               1
#define AIC_SC_REG_BIU_NON_SECURE_OFFSET            28
#define AIC_SC_REG_BIU_PRIVILEGE_LEN                1
#define AIC_SC_REG_BIU_PRIVILEGE_OFFSET             27
#define AIC_SC_REG_DISABLE_RAM_CLEAR_LEN            1
#define AIC_SC_REG_DISABLE_RAM_CLEAR_OFFSET         26
#define AIC_SC_REG_LITE_TINY_LEN                    1
#define AIC_SC_REG_LITE_TINY_OFFSET                 25
#define AIC_SC_REG_TASK_RESTORE_LEN                 1
#define AIC_SC_REG_TASK_RESTORE_OFFSET              24
#define AIC_SC_REG_L2_IN_MAIN_LEN                   8
#define AIC_SC_REG_L2_IN_MAIN_OFFSET                16
#define AIC_SC_REG_BLOCK_DIM_LEN                    16
#define AIC_SC_REG_BLOCK_DIM_OFFSET                 0

#define AIC_SC_REG_DATA_MAIN_BASE_0_LEN    32
#define AIC_SC_REG_DATA_MAIN_BASE_0_OFFSET 0

#define AIC_SC_REG_DATA_MAIN_BASE_1_LEN    16
#define AIC_SC_REG_DATA_MAIN_BASE_1_OFFSET 16
#define AIC_SC_REG_PCIE_AXUSER_LEN         16
#define AIC_SC_REG_PCIE_AXUSER_OFFSET      0

#define AIC_SC_REG_KIS_THREAD_DIM_LEN    16
#define AIC_SC_REG_KIS_THREAD_DIM_OFFSET 16
#define AIC_SC_REG_KIS_THREAD_ID_LEN     16
#define AIC_SC_REG_KIS_THREAD_ID_OFFSET  0

#define AIC_SC_REG_SUB_BLOCK_DIM_LEN    16
#define AIC_SC_REG_SUB_BLOCK_DIM_OFFSET 16
#define AIC_SC_REG_SUB_BLOCK_ID_LEN     16
#define AIC_SC_REG_SUB_BLOCK_ID_OFFSET  0

#define AIC_SC_REG_DATA_SIZE_LEN    31
#define AIC_SC_REG_DATA_SIZE_OFFSET 1
#define AIC_SC_REG_STA_MODE_LEN     1
#define AIC_SC_REG_STA_MODE_OFFSET  0

#define AIC_SC_REG_WRR_RATIO_WR_LEN         2
#define AIC_SC_REG_WRR_RATIO_WR_OFFSET      26
#define AIC_SC_REG_WRR_RATIO_RD_LEN         2
#define AIC_SC_REG_WRR_RATIO_RD_OFFSET      24
#define AIC_SC_REG_E2E_FLOW_CTRL_NS_LEN     1
#define AIC_SC_REG_E2E_FLOW_CTRL_NS_OFFSET  22
#define AIC_SC_REG_E2E_FLOW_CTRL_PMG_LEN    2
#define AIC_SC_REG_E2E_FLOW_CTRL_PMG_OFFSET 20
#define AIC_SC_REG_CFG_AX_QOS_LEN           4
#define AIC_SC_REG_CFG_AX_QOS_OFFSET        16
#define AIC_SC_REG_PARTID_FOR_INST_LEN      8
#define AIC_SC_REG_PARTID_FOR_INST_OFFSET   8
#define AIC_SC_REG_PARTID_FOR_DATA_LEN      8
#define AIC_SC_REG_PARTID_FOR_DATA_OFFSET   0

#define AIC_SC_REG_L2_REMAP_CFG0_0_LEN    32
#define AIC_SC_REG_L2_REMAP_CFG0_0_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG0_1_LEN    32
#define AIC_SC_REG_L2_REMAP_CFG0_1_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG1_0_LEN    32
#define AIC_SC_REG_L2_REMAP_CFG1_0_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG1_1_LEN    32
#define AIC_SC_REG_L2_REMAP_CFG1_1_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG2_0_LEN    32
#define AIC_SC_REG_L2_REMAP_CFG2_0_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG2_1_LEN    32
#define AIC_SC_REG_L2_REMAP_CFG2_1_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG3_0_LEN    32
#define AIC_SC_REG_L2_REMAP_CFG3_0_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG3_1_LEN    32
#define AIC_SC_REG_L2_REMAP_CFG3_1_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG4_0_LEN    32
#define AIC_SC_REG_L2_REMAP_CFG4_0_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG4_1_LEN    32
#define AIC_SC_REG_L2_REMAP_CFG4_1_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG5_0_LEN    32
#define AIC_SC_REG_L2_REMAP_CFG5_0_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG5_1_LEN    32
#define AIC_SC_REG_L2_REMAP_CFG5_1_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG6_0_LEN    32
#define AIC_SC_REG_L2_REMAP_CFG6_0_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG6_1_LEN    32
#define AIC_SC_REG_L2_REMAP_CFG6_1_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG7_0_LEN    32
#define AIC_SC_REG_L2_REMAP_CFG7_0_OFFSET 0

#define AIC_SC_REG_L2_REMAP_CFG7_1_LEN    32
#define AIC_SC_REG_L2_REMAP_CFG7_1_OFFSET 0

#define AIC_SC_REG_STACK_PHY_BASE_0_LEN    32
#define AIC_SC_REG_STACK_PHY_BASE_0_OFFSET 0

#define AIC_SC_REG_STACK_PHY_BASE_1_LEN    17
#define AIC_SC_REG_STACK_PHY_BASE_1_OFFSET 0

#define AIC_SC_REG_DBG_RW_DONE_LEN    1
#define AIC_SC_REG_DBG_RW_DONE_OFFSET 8
#define AIC_SC_REG_DBG_CTRL_RD_LEN    1
#define AIC_SC_REG_DBG_CTRL_RD_OFFSET 1
#define AIC_SC_REG_DBG_CTRL_WR_LEN    1
#define AIC_SC_REG_DBG_CTRL_WR_OFFSET 0

#define AIC_SC_REG_DBG_ADDR_0_LEN    32
#define AIC_SC_REG_DBG_ADDR_0_OFFSET 0

#define AIC_SC_REG_DFX_EN_LEN        1
#define AIC_SC_REG_DFX_EN_OFFSET     31
#define AIC_SC_REG_DBG_SEL_LEN       15
#define AIC_SC_REG_DBG_SEL_OFFSET    16
#define AIC_SC_REG_DBG_ADDR_1_LEN    16
#define AIC_SC_REG_DBG_ADDR_1_OFFSET 0

#define AIC_SC_REG_DBG_DATA0_0_LEN    32
#define AIC_SC_REG_DBG_DATA0_0_OFFSET 0

#define AIC_SC_REG_DBG_DATA0_1_LEN    32
#define AIC_SC_REG_DBG_DATA0_1_OFFSET 0

#define AIC_SC_REG_DBG_DATA1_0_LEN    32
#define AIC_SC_REG_DBG_DATA1_0_OFFSET 0

#define AIC_SC_REG_DBG_DATA1_1_LEN    32
#define AIC_SC_REG_DBG_DATA1_1_OFFSET 0

#define AIC_SC_REG_DBG_DATA2_0_LEN    32
#define AIC_SC_REG_DBG_DATA2_0_OFFSET 0

#define AIC_SC_REG_DBG_DATA2_1_LEN    32
#define AIC_SC_REG_DBG_DATA2_1_OFFSET 0

#define AIC_SC_REG_DBG_DATA3_0_LEN    32
#define AIC_SC_REG_DBG_DATA3_0_OFFSET 0

#define AIC_SC_REG_DBG_DATA3_1_LEN    32
#define AIC_SC_REG_DBG_DATA3_1_OFFSET 0

#define AIC_SC_REG_DFX_DATA_LEN    8
#define AIC_SC_REG_DFX_DATA_OFFSET 0

#define AIC_SC_REG_DBG_IFU_RESUME_FETCH_ONE_LEN    1
#define AIC_SC_REG_DBG_IFU_RESUME_FETCH_ONE_OFFSET 31
#define AIC_SC_REG_DBG_IFU_RESUME_ALL_LEN          1
#define AIC_SC_REG_DBG_IFU_RESUME_ALL_OFFSET       30

#define AIC_SC_REG_DBG_READ_ERR_LEN         1
#define AIC_SC_REG_DBG_READ_ERR_OFFSET      2
#define AIC_SC_REG_DBG_ACCESS_FAIL_LEN      1
#define AIC_SC_REG_DBG_ACCESS_FAIL_OFFSET   1
#define AIC_SC_REG_DBG_CACHE_INVALID_LEN    1
#define AIC_SC_REG_DBG_CACHE_INVALID_OFFSET 0

#define AIC_SC_REG_RESERVED_REG00_0_LEN         17
#define AIC_SC_REG_RESERVED_REG00_0_OFFSET      15
#define AIC_SC_REG_MTE2_2D_FUSE_EN_N_LEN        1
#define AIC_SC_REG_MTE2_2D_FUSE_EN_N_OFFSET     14
#define AIC_SC_REG_MTE2_DM_FUSE_EN_N_LEN        1
#define AIC_SC_REG_MTE2_DM_FUSE_EN_N_OFFSET     13
#define AIC_SC_REG_MTE3_DM_FUSE_EN_N_LEN        1
#define AIC_SC_REG_MTE3_DM_FUSE_EN_N_OFFSET     12
#define AIC_SC_REG_MTE2_L0A_ERLY_ST_EN_N_LEN    1
#define AIC_SC_REG_MTE2_L0A_ERLY_ST_EN_N_OFFSET 11
#define AIC_SC_REG_MTE2_L0B_ERLY_ST_EN_N_LEN    1
#define AIC_SC_REG_MTE2_L0B_ERLY_ST_EN_N_OFFSET 10
#define AIC_SC_REG_MTE2_L1_ERLY_ST_EN_N_LEN     1
#define AIC_SC_REG_MTE2_L1_ERLY_ST_EN_N_OFFSET  9
#define AIC_SC_REG_MTE2_UB_ERLY_ST_EN_N_LEN     1
#define AIC_SC_REG_MTE2_UB_ERLY_ST_EN_N_OFFSET  8
#define AIC_SC_REG_SCAT_BP_EN_N_LEN             1
#define AIC_SC_REG_SCAT_BP_EN_N_OFFSET          7
#define AIC_SC_REG_MTE2_UZP_ERLY_ST_EN_N_LEN    1
#define AIC_SC_REG_MTE2_UZP_ERLY_ST_EN_N_OFFSET 6
#define AIC_SC_REG_MTE2_FMD_ERLY_ST_EN_N_LEN    1
#define AIC_SC_REG_MTE2_FMD_ERLY_ST_EN_N_OFFSET 5
#define AIC_SC_REG_MTE3_FMC_ERLY_ST_EN_N_LEN    1
#define AIC_SC_REG_MTE3_FMC_ERLY_ST_EN_N_OFFSET 4
#define AIC_SC_REG_MTE3_DM_ERLY_ST_EN_N_LEN     1
#define AIC_SC_REG_MTE3_DM_ERLY_ST_EN_N_OFFSET  3
#define AIC_SC_REG_MTE3_ALL_FUSE_EN_N_LEN       1
#define AIC_SC_REG_MTE3_ALL_FUSE_EN_N_OFFSET    2
#define AIC_SC_REG_MTE2_CMPLX_FUSE_EN_N_LEN     1
#define AIC_SC_REG_MTE2_CMPLX_FUSE_EN_N_OFFSET  1
#define AIC_SC_REG_MTE2_NORM_FUSE_EN_N_LEN      1
#define AIC_SC_REG_MTE2_NORM_FUSE_EN_N_OFFSET   0

#define AIC_SC_REG_RESERVED_REG00_1_LEN    32
#define AIC_SC_REG_RESERVED_REG00_1_OFFSET 0

#define AIC_SC_REG_RESERVED_REG01_0_LEN    32
#define AIC_SC_REG_RESERVED_REG01_0_OFFSET 0

#define AIC_SC_REG_RESERVED_REG01_1_LEN    32
#define AIC_SC_REG_RESERVED_REG01_1_OFFSET 0

#define AIC_SC_REG_DJTAG_CLK_BYPASS_EN_LEN    1
#define AIC_SC_REG_DJTAG_CLK_BYPASS_EN_OFFSET 0

#define AIC_SC_REG_HW_BKPT0_ID_2_LEN    16
#define AIC_SC_REG_HW_BKPT0_ID_2_OFFSET 0

#define AIC_SC_REG_HW_BKPT1_ID_2_LEN    16
#define AIC_SC_REG_HW_BKPT1_ID_2_OFFSET 0

#define AIC_SC_REG_HW_BKPT2_ID_2_LEN    16
#define AIC_SC_REG_HW_BKPT2_ID_2_OFFSET 0

#define AIC_SC_REG_HW_BKPT3_ID_2_LEN    16
#define AIC_SC_REG_HW_BKPT3_ID_2_OFFSET 0

























#define AIC_SC_REG_PMU_CTRL_RESERVED_0_LEN    23
#define AIC_SC_REG_PMU_CTRL_RESERVED_0_OFFSET 9
#define AIC_SC_REG_PMU_OVERFLOW_LEN           1
#define AIC_SC_REG_PMU_OVERFLOW_OFFSET        8
#define AIC_SC_REG_AIC_TASK_CYC_CNT_EN_LEN    1
#define AIC_SC_REG_AIC_TASK_CYC_CNT_EN_OFFSET 3
#define AIC_SC_REG_SAMPLE_PROFILE_MODE_LEN    1
#define AIC_SC_REG_SAMPLE_PROFILE_MODE_OFFSET 2
#define AIC_SC_REG_USER_PROFILE_MODE_LEN      1
#define AIC_SC_REG_USER_PROFILE_MODE_OFFSET   1
#define AIC_SC_REG_PMU_EN_LEN                 1
#define AIC_SC_REG_PMU_EN_OFFSET              0

#define AIC_SC_REG_PMU_CTRL_RESERVED_1_LEN    32
#define AIC_SC_REG_PMU_CTRL_RESERVED_1_OFFSET 0

#define AIC_SC_REG_PMU_MIN_OV_CNT_0_LEN    32
#define AIC_SC_REG_PMU_MIN_OV_CNT_0_OFFSET 0

#define AIC_SC_REG_PMU_MIN_OV_CNT_1_LEN    32
#define AIC_SC_REG_PMU_MIN_OV_CNT_1_OFFSET 0

#define AIC_SC_REG_PMU_CNT0_LEN    32
#define AIC_SC_REG_PMU_CNT0_OFFSET 0

#define AIC_SC_REG_PMU_CNT1_LEN    32
#define AIC_SC_REG_PMU_CNT1_OFFSET 0

#define AIC_SC_REG_PMU_CNT2_LEN    32
#define AIC_SC_REG_PMU_CNT2_OFFSET 0

#define AIC_SC_REG_PMU_CNT3_LEN    32
#define AIC_SC_REG_PMU_CNT3_OFFSET 0

#define AIC_SC_REG_PMU_CNT4_LEN    32
#define AIC_SC_REG_PMU_CNT4_OFFSET 0

#define AIC_SC_REG_PMU_CNT5_LEN    32
#define AIC_SC_REG_PMU_CNT5_OFFSET 0

#define AIC_SC_REG_PMU_CNT6_LEN    32
#define AIC_SC_REG_PMU_CNT6_OFFSET 0

#define AIC_SC_REG_PMU_CNT7_LEN    32
#define AIC_SC_REG_PMU_CNT7_OFFSET 0

#define AIC_SC_REG_PMU_TASK_CYC_CNT_0_LEN    32
#define AIC_SC_REG_PMU_TASK_CYC_CNT_0_OFFSET 0

#define AIC_SC_REG_PMU_TASK_CYC_CNT_1_LEN    32
#define AIC_SC_REG_PMU_TASK_CYC_CNT_1_OFFSET 0





















#define AIC_SC_REG_PMU_START_CNT_CYC_0_LEN    32
#define AIC_SC_REG_PMU_START_CNT_CYC_0_OFFSET 0

#define AIC_SC_REG_PMU_START_CNT_CYC_1_LEN    32
#define AIC_SC_REG_PMU_START_CNT_CYC_1_OFFSET 0

#define AIC_SC_REG_PMU_STOP_CNT_CYC_0_LEN    32
#define AIC_SC_REG_PMU_STOP_CNT_CYC_0_OFFSET 0

#define AIC_SC_REG_PMU_STOP_CNT_CYC_1_LEN    32
#define AIC_SC_REG_PMU_STOP_CNT_CYC_1_OFFSET 0

#define AIC_SC_REG_AIC_TASK_CYC_CNT_0_LEN    32
#define AIC_SC_REG_AIC_TASK_CYC_CNT_0_OFFSET 0

#define AIC_SC_REG_AIC_TASK_CYC_CNT_1_LEN    32
#define AIC_SC_REG_AIC_TASK_CYC_CNT_1_OFFSET 0

#define AIC_SC_REG_IFU_RESERVED_REG_0_LEN           11
#define AIC_SC_REG_IFU_RESERVED_REG_0_OFFSET        21
#define AIC_SC_REG_IFU_PREFET_OST_LMT_LEN           5
#define AIC_SC_REG_IFU_PREFET_OST_LMT_OFFSET        16
#define AIC_SC_REG_IFU_READ_MERGE_EN_LEN            1
#define AIC_SC_REG_IFU_READ_MERGE_EN_OFFSET         8
#define AIC_SC_REG_IFU_EXIT_FROM_EXCEPT_STOP_LEN    1
#define AIC_SC_REG_IFU_EXIT_FROM_EXCEPT_STOP_OFFSET 7
#define AIC_SC_REG_IFU_SW_HW_STALL_SEL_LEN          1
#define AIC_SC_REG_IFU_SW_HW_STALL_SEL_OFFSET       6
#define AIC_SC_REG_IFU_SW_STALL_LEN                 1
#define AIC_SC_REG_IFU_SW_STALL_OFFSET              5
#define AIC_SC_REG_IFU_EXCEPTION_BACK_EN_LEN        1
#define AIC_SC_REG_IFU_EXCEPTION_BACK_EN_OFFSET     4
#define AIC_SC_REG_IFU_PRIORITY_PUSH_EN_LEN         1
#define AIC_SC_REG_IFU_PRIORITY_PUSH_EN_OFFSET      3
#define AIC_SC_REG_IFU_PREFETCH_EN1_LEN             1
#define AIC_SC_REG_IFU_PREFETCH_EN1_OFFSET          2
#define AIC_SC_REG_IFU_IC_EN_LEN                    1
#define AIC_SC_REG_IFU_IC_EN_OFFSET                 1
#define AIC_SC_REG_IFU_PREFETCH_EN_LEN              1
#define AIC_SC_REG_IFU_PREFETCH_EN_OFFSET           0

#define AIC_SC_REG_IFU_RESERVED_REG_1_LEN    32
#define AIC_SC_REG_IFU_RESERVED_REG_1_OFFSET 0

#define AIC_SC_REG_ALL_CACHE_INV_REQ_LEN    1
#define AIC_SC_REG_ALL_CACHE_INV_REQ_OFFSET 4
#define AIC_SC_REG_IFU_PRELOAD_STOP_LEN     1
#define AIC_SC_REG_IFU_PRELOAD_STOP_OFFSET  3
#define AIC_SC_REG_IFU_PRELOAD_REQ_LEN      1
#define AIC_SC_REG_IFU_PRELOAD_REQ_OFFSET   2
#define AIC_SC_REG_IC_INV_ALL_LEN           1
#define AIC_SC_REG_IC_INV_ALL_OFFSET        1
#define AIC_SC_REG_IC_INV_ONE_LEN           1
#define AIC_SC_REG_IC_INV_ONE_OFFSET        0

#define AIC_SC_REG_IC_INV_VA_0_LEN    25
#define AIC_SC_REG_IC_INV_VA_0_OFFSET 7

#define AIC_SC_REG_IC_INV_VA_1_LEN    16
#define AIC_SC_REG_IC_INV_VA_1_OFFSET 0

#define AIC_SC_REG_INV_DONE_LEN    1
#define AIC_SC_REG_INV_DONE_OFFSET 0

#define AIC_SC_REG_HW_BKPT_EN_LEN    4
#define AIC_SC_REG_HW_BKPT_EN_OFFSET 0

#define AIC_SC_REG_HW_BKPT0_PC_0_LEN    30
#define AIC_SC_REG_HW_BKPT0_PC_0_OFFSET 2

#define AIC_SC_REG_HW_BKPT0_ID_LEN      16
#define AIC_SC_REG_HW_BKPT0_ID_OFFSET   16
#define AIC_SC_REG_HW_BKPT0_PC_1_LEN    16
#define AIC_SC_REG_HW_BKPT0_PC_1_OFFSET 0

#define AIC_SC_REG_HW_BKPT1_PC_0_LEN    30
#define AIC_SC_REG_HW_BKPT1_PC_0_OFFSET 2

#define AIC_SC_REG_HW_BKPT1_ID_LEN      16
#define AIC_SC_REG_HW_BKPT1_ID_OFFSET   16
#define AIC_SC_REG_HW_BKPT1_PC_1_LEN    16
#define AIC_SC_REG_HW_BKPT1_PC_1_OFFSET 0

#define AIC_SC_REG_HW_BKPT2_PC_0_LEN    30
#define AIC_SC_REG_HW_BKPT2_PC_0_OFFSET 2

#define AIC_SC_REG_HW_BKPT2_ID_LEN      16
#define AIC_SC_REG_HW_BKPT2_ID_OFFSET   16
#define AIC_SC_REG_HW_BKPT2_PC_1_LEN    16
#define AIC_SC_REG_HW_BKPT2_PC_1_OFFSET 0

#define AIC_SC_REG_HW_BKPT3_PC_0_LEN    30
#define AIC_SC_REG_HW_BKPT3_PC_0_OFFSET 2

#define AIC_SC_REG_HW_BKPT3_ID_LEN      16
#define AIC_SC_REG_HW_BKPT3_ID_OFFSET   16
#define AIC_SC_REG_HW_BKPT3_PC_1_LEN    16
#define AIC_SC_REG_HW_BKPT3_PC_1_OFFSET 0

















































#define AIC_SC_REG_CCU_IQ_TIMEOUT_LEN    32
#define AIC_SC_REG_CCU_IQ_TIMEOUT_OFFSET 0

#define AIC_SC_REG_CCU_RESERVED_REG_0_LEN              6
#define AIC_SC_REG_CCU_RESERVED_REG_0_OFFSET           26
#define AIC_SC_REG_SU_RECORD_1ST_OVFLW_PC_EN_LEN       1
#define AIC_SC_REG_SU_RECORD_1ST_OVFLW_PC_EN_OFFSET    25
#define AIC_SC_REG_SU_LSU_FETCHER_PRIORITY_LEN         1
#define AIC_SC_REG_SU_LSU_FETCHER_PRIORITY_OFFSET      24
#define AIC_SC_REG_SU_LSU_FETCHER_LINE_DISP_NUM_LEN    3
#define AIC_SC_REG_SU_LSU_FETCHER_LINE_DISP_NUM_OFFSET 21
#define AIC_SC_REG_SU_LSU_FETCHER_OST_CNT_LMT_LEN      4
#define AIC_SC_REG_SU_LSU_FETCHER_OST_CNT_LMT_OFFSET   17
#define AIC_SC_REG_SU_LSU_FETCHER_FETCHNUM_LEN         3
#define AIC_SC_REG_SU_LSU_FETCHER_FETCHNUM_OFFSET      14
#define AIC_SC_REG_SU_LSU_FETCHER_EN_LEN               1
#define AIC_SC_REG_SU_LSU_FETCHER_EN_OFFSET            13
#define AIC_SC_REG_SU_STACK_BUFFER_MODE_LEN            1
#define AIC_SC_REG_SU_STACK_BUFFER_MODE_OFFSET         12
#define AIC_SC_REG_FIXP_SINGLE_COMMIT_LEN              1
#define AIC_SC_REG_FIXP_SINGLE_COMMIT_OFFSET           11
#define AIC_SC_REG_CCU_DC_SINGLE_COMMIT_LEN            1
#define AIC_SC_REG_CCU_DC_SINGLE_COMMIT_OFFSET         10
#define AIC_SC_REG_MTE5_SINGLE_COMMIT_LEN              1
#define AIC_SC_REG_MTE5_SINGLE_COMMIT_OFFSET           9
#define AIC_SC_REG_MTE4_SINGLE_COMMIT_LEN              1
#define AIC_SC_REG_MTE4_SINGLE_COMMIT_OFFSET           8
#define AIC_SC_REG_CCU_RFF_BP_EN_LEN                   1
#define AIC_SC_REG_CCU_RFF_BP_EN_OFFSET                7
#define AIC_SC_REG_GLOBAL_SINGLE_COMMIT_LEN            1
#define AIC_SC_REG_GLOBAL_SINGLE_COMMIT_OFFSET         6
#define AIC_SC_REG_CUBE_SINGLE_COMMIT_LEN              1
#define AIC_SC_REG_CUBE_SINGLE_COMMIT_OFFSET           5
#define AIC_SC_REG_VEC_SINGLE_COMMIT_LEN               1
#define AIC_SC_REG_VEC_SINGLE_COMMIT_OFFSET            4
#define AIC_SC_REG_MTE3_SINGLE_COMMIT_LEN              1
#define AIC_SC_REG_MTE3_SINGLE_COMMIT_OFFSET           3
#define AIC_SC_REG_MTE2_SINGLE_COMMIT_LEN              1
#define AIC_SC_REG_MTE2_SINGLE_COMMIT_OFFSET           2
#define AIC_SC_REG_MTE1_SINGLE_COMMIT_LEN              1
#define AIC_SC_REG_MTE1_SINGLE_COMMIT_OFFSET           1
#define AIC_SC_REG_CCU_SINGLE_ISSUE_MODE_LEN           1
#define AIC_SC_REG_CCU_SINGLE_ISSUE_MODE_OFFSET        0

#define AIC_SC_REG_CCU_RESERVED_REG_1_LEN    32
#define AIC_SC_REG_CCU_RESERVED_REG_1_OFFSET 0

#define AIC_SC_REG_CLK_SU_IQ_DELAY_CNT_LEN      5
#define AIC_SC_REG_CLK_SU_IQ_DELAY_CNT_OFFSET   5
#define AIC_SC_REG_CLK_SU_FIXP_DELAY_CNT_LEN    5
#define AIC_SC_REG_CLK_SU_FIXP_DELAY_CNT_OFFSET 0

#define AIC_SC_REG_SU_STB_TIMEOUT_EN_LEN     1
#define AIC_SC_REG_SU_STB_TIMEOUT_EN_OFFSET  31
#define AIC_SC_REG_SU_STB_TIMEOUT_CNT_LEN    10
#define AIC_SC_REG_SU_STB_TIMEOUT_CNT_OFFSET 0

#define AIC_SC_REG_RO_SPR_STATUS_0_LEN    32
#define AIC_SC_REG_RO_SPR_STATUS_0_OFFSET 0

#define AIC_SC_REG_RO_SPR_STATUS_1_LEN    32
#define AIC_SC_REG_RO_SPR_STATUS_1_OFFSET 0





#define AIC_SC_REG_CCU_COND_SPR_0_LEN    32
#define AIC_SC_REG_CCU_COND_SPR_0_OFFSET 0

#define AIC_SC_REG_CCU_COND_SPR_1_LEN    32
#define AIC_SC_REG_CCU_COND_SPR_1_OFFSET 0

#define AIC_SC_REG_REDIRECT_IFU_STATUS_LEN    1
#define AIC_SC_REG_REDIRECT_IFU_STATUS_OFFSET 0

#define AIC_SC_REG_CROSS_CORE_FLAG15_LEN    1
#define AIC_SC_REG_CROSS_CORE_FLAG15_OFFSET 15
#define AIC_SC_REG_CROSS_CORE_FLAG14_LEN    1
#define AIC_SC_REG_CROSS_CORE_FLAG14_OFFSET 14
#define AIC_SC_REG_CROSS_CORE_FLAG13_LEN    1
#define AIC_SC_REG_CROSS_CORE_FLAG13_OFFSET 13
#define AIC_SC_REG_CROSS_CORE_FLAG12_LEN    1
#define AIC_SC_REG_CROSS_CORE_FLAG12_OFFSET 12
#define AIC_SC_REG_CROSS_CORE_FLAG11_LEN    1
#define AIC_SC_REG_CROSS_CORE_FLAG11_OFFSET 11
#define AIC_SC_REG_CROSS_CORE_FLAG10_LEN    1
#define AIC_SC_REG_CROSS_CORE_FLAG10_OFFSET 10
#define AIC_SC_REG_CROSS_CORE_FLAG9_LEN     1
#define AIC_SC_REG_CROSS_CORE_FLAG9_OFFSET  9
#define AIC_SC_REG_CROSS_CORE_FLAG8_LEN     1
#define AIC_SC_REG_CROSS_CORE_FLAG8_OFFSET  8
#define AIC_SC_REG_CROSS_CORE_FLAG7_LEN     1
#define AIC_SC_REG_CROSS_CORE_FLAG7_OFFSET  7
#define AIC_SC_REG_CROSS_CORE_FLAG6_LEN     1
#define AIC_SC_REG_CROSS_CORE_FLAG6_OFFSET  6
#define AIC_SC_REG_CROSS_CORE_FLAG5_LEN     1
#define AIC_SC_REG_CROSS_CORE_FLAG5_OFFSET  5
#define AIC_SC_REG_CROSS_CORE_FLAG4_LEN     1
#define AIC_SC_REG_CROSS_CORE_FLAG4_OFFSET  4
#define AIC_SC_REG_CROSS_CORE_FLAG3_LEN     1
#define AIC_SC_REG_CROSS_CORE_FLAG3_OFFSET  3
#define AIC_SC_REG_CROSS_CORE_FLAG2_LEN     1
#define AIC_SC_REG_CROSS_CORE_FLAG2_OFFSET  2
#define AIC_SC_REG_CROSS_CORE_FLAG1_LEN     1
#define AIC_SC_REG_CROSS_CORE_FLAG1_OFFSET  1
#define AIC_SC_REG_CROSS_CORE_FLAG0_LEN     1
#define AIC_SC_REG_CROSS_CORE_FLAG0_OFFSET  0

#define AIC_SC_REG_BIU_CTRL0_0_LEN    32
#define AIC_SC_REG_BIU_CTRL0_0_OFFSET 0

#define AIC_SC_REG_BIU_CTRL0_1_LEN    32
#define AIC_SC_REG_BIU_CTRL0_1_OFFSET 0

#define AIC_SC_REG_BIU_CTRL1_0_LEN    32
#define AIC_SC_REG_BIU_CTRL1_0_OFFSET 0

#define AIC_SC_REG_BIU_CTRL1_1_LEN    32
#define AIC_SC_REG_BIU_CTRL1_1_OFFSET 0

#define AIC_SC_REG_BIU_CTRL2_0_LEN    32
#define AIC_SC_REG_BIU_CTRL2_0_OFFSET 0

#define AIC_SC_REG_BIU_CTRL2_1_LEN    32
#define AIC_SC_REG_BIU_CTRL2_1_OFFSET 0

#define AIC_SC_REG_BIU_STATUS0_0_LEN    32
#define AIC_SC_REG_BIU_STATUS0_0_OFFSET 0

#define AIC_SC_REG_BIU_STATUS0_1_LEN    32
#define AIC_SC_REG_BIU_STATUS0_1_OFFSET 0

#define AIC_SC_REG_BIU_STATUS1_0_LEN    32
#define AIC_SC_REG_BIU_STATUS1_0_OFFSET 0

#define AIC_SC_REG_BIU_STATUS1_1_LEN    32
#define AIC_SC_REG_BIU_STATUS1_1_OFFSET 0

#define AIC_SC_REG_BIU_STATUS2_0_LEN    32
#define AIC_SC_REG_BIU_STATUS2_0_OFFSET 0

#define AIC_SC_REG_BIU_STATUS2_1_LEN    32
#define AIC_SC_REG_BIU_STATUS2_1_OFFSET 0

#define AIC_SC_REG_BIU_STATUS3_0_LEN    32
#define AIC_SC_REG_BIU_STATUS3_0_OFFSET 0

#define AIC_SC_REG_BIU_STATUS3_1_LEN    32
#define AIC_SC_REG_BIU_STATUS3_1_OFFSET 0

#define AIC_SC_REG_BIU_STATUS4_0_LEN    32
#define AIC_SC_REG_BIU_STATUS4_0_OFFSET 0

#define AIC_SC_REG_BIU_STATUS4_1_LEN    32
#define AIC_SC_REG_BIU_STATUS4_1_OFFSET 0

#define AIC_SC_REG_BIU_STATUS5_0_LEN    32
#define AIC_SC_REG_BIU_STATUS5_0_OFFSET 0

#define AIC_SC_REG_BIU_STATUS5_1_LEN    32
#define AIC_SC_REG_BIU_STATUS5_1_OFFSET 0

#define AIC_SC_REG_BIU_SMMU_STREAMID_LEN    16
#define AIC_SC_REG_BIU_SMMU_STREAMID_OFFSET 0

#define AIC_SC_REG_BIU_L2_PADDR_BASE_0_LEN    32
#define AIC_SC_REG_BIU_L2_PADDR_BASE_0_OFFSET 0

#define AIC_SC_REG_BIU_L2_PADDR_BASE_1_LEN    32
#define AIC_SC_REG_BIU_L2_PADDR_BASE_1_OFFSET 0

#define AIC_SC_REG_BIU_L2_SIZE_LEN    4
#define AIC_SC_REG_BIU_L2_SIZE_OFFSET 0

#define AIC_SC_REG_BIU_L2_REMAP_EN_LEN    1
#define AIC_SC_REG_BIU_L2_REMAP_EN_OFFSET 31

#define AIC_SC_REG_BIU_L2_PAGE_SIZE_LEN    4
#define AIC_SC_REG_BIU_L2_PAGE_SIZE_OFFSET 0

#define AIC_SC_REG_BIU_CTRL6_0_LEN    32
#define AIC_SC_REG_BIU_CTRL6_0_OFFSET 0

#define AIC_SC_REG_BIU_CTRL6_1_LEN    32
#define AIC_SC_REG_BIU_CTRL6_1_OFFSET 0

#define AIC_SC_REG_BIU_STATUS8_0_LEN    32
#define AIC_SC_REG_BIU_STATUS8_0_OFFSET 0

#define AIC_SC_REG_BIU_STATUS8_1_LEN    32
#define AIC_SC_REG_BIU_STATUS8_1_OFFSET 0

#define AIC_SC_REG_BIU_STREAM_NS_LEN    1
#define AIC_SC_REG_BIU_STREAM_NS_OFFSET 0

#define AIC_SC_REG_PQOS_OTSD2_LVL_LEN    8
#define AIC_SC_REG_PQOS_OTSD2_LVL_OFFSET 16
#define AIC_SC_REG_PQOS_OTSD1_LVL_LEN    8
#define AIC_SC_REG_PQOS_OTSD1_LVL_OFFSET 8
#define AIC_SC_REG_PQOS_OTSD0_LVL_LEN    8
#define AIC_SC_REG_PQOS_OTSD0_LVL_OFFSET 0

#define AIC_SC_REG_WOSD_DC_TH_LEN        3
#define AIC_SC_REG_WOSD_DC_TH_OFFSET     28
#define AIC_SC_REG_WOSD_CTRL_EN_LEN      2
#define AIC_SC_REG_WOSD_CTRL_EN_OFFSET   24
#define AIC_SC_REG_ROSD_MTE_TH_LEN       7
#define AIC_SC_REG_ROSD_MTE_TH_OFFSET    16
#define AIC_SC_REG_ROSD_DC_TH_LEN        3
#define AIC_SC_REG_ROSD_DC_TH_OFFSET     12
#define AIC_SC_REG_ROSD_IFU_TH_LEN       3
#define AIC_SC_REG_ROSD_IFU_TH_OFFSET    8
#define AIC_SC_REG_ROSD_CTRL_EN_LEN      4
#define AIC_SC_REG_ROSD_CTRL_EN_OFFSET   4
#define AIC_SC_REG_ADDR_INTLV_CFG_LEN    2
#define AIC_SC_REG_ADDR_INTLV_CFG_OFFSET 1

#define AIC_SC_REG_ROSD_ISTV_TH_LEN    3
#define AIC_SC_REG_ROSD_ISTV_TH_OFFSET 8
#define AIC_SC_REG_WOSD_MTE_TH_LEN     6
#define AIC_SC_REG_WOSD_MTE_TH_OFFSET  0

#define AIC_SC_REG_SMMU_STREAMID_BP_LEN    16
#define AIC_SC_REG_SMMU_STREAMID_BP_OFFSET 16
#define AIC_SC_REG_SMMU_SSIDV_BP_LEN       1
#define AIC_SC_REG_SMMU_SSIDV_BP_OFFSET    3
#define AIC_SC_REG_SMMU_SSIDV_UNBP_LEN     1
#define AIC_SC_REG_SMMU_SSIDV_UNBP_OFFSET  2
#define AIC_SC_REG_SMMU_BP_SEL_LEN         2
#define AIC_SC_REG_SMMU_BP_SEL_OFFSET      0

#define AIC_SC_REG_SMMU_SEC_STRMID_BP_LEN      16
#define AIC_SC_REG_SMMU_SEC_STRMID_BP_OFFSET   16
#define AIC_SC_REG_SMMU_SEC_STRMID_UNBP_LEN    16
#define AIC_SC_REG_SMMU_SEC_STRMID_UNBP_OFFSET 0

#define AIC_SC_REG_SC_BIU_ASIL_LEN    3
#define AIC_SC_REG_SC_BIU_ASIL_OFFSET 0

#define AIC_SC_REG_BIU_PARTID_QOS_ENABLE_LEN    1
#define AIC_SC_REG_BIU_PARTID_QOS_ENABLE_OFFSET 31
#define AIC_SC_REG_BIU_PARTID_FOR_INST_LEN      8
#define AIC_SC_REG_BIU_PARTID_FOR_INST_OFFSET   8
#define AIC_SC_REG_BIU_PARTID_FOR_DATA_LEN      8
#define AIC_SC_REG_BIU_PARTID_FOR_DATA_OFFSET   0

#define AIC_SC_REG_BIU_AXPROT_PERF_LEN    3
#define AIC_SC_REG_BIU_AXPROT_PERF_OFFSET 0

#define AIC_SC_REG_BIU_STATUS9_0_LEN    32
#define AIC_SC_REG_BIU_STATUS9_0_OFFSET 0

#define AIC_SC_REG_BIU_STATUS9_1_LEN    32
#define AIC_SC_REG_BIU_STATUS9_1_OFFSET 0

#define AIC_SC_REG_AXI_SOFTRST_STATE0_2_LEN    32
#define AIC_SC_REG_AXI_SOFTRST_STATE0_2_OFFSET 0

#define AIC_SC_REG_AXI_SOFTRST_STATE1_2_LEN    32
#define AIC_SC_REG_AXI_SOFTRST_STATE1_2_OFFSET 0

#define AIC_SC_REG_AXI_SOFTRST_STATE0_3_LEN    32
#define AIC_SC_REG_AXI_SOFTRST_STATE0_3_OFFSET 0

#define AIC_SC_REG_AXI_SOFTRST_STATE1_3_LEN    32
#define AIC_SC_REG_AXI_SOFTRST_STATE1_3_OFFSET 0

#define AIC_SC_REG_BIU_TH_DIRECT_LEN    2
#define AIC_SC_REG_BIU_TH_DIRECT_OFFSET 0

#define AIC_SC_REG_CORE_ID_LEN    16
#define AIC_SC_REG_CORE_ID_OFFSET 0

#define AIC_SC_REG_AIC_TAG_VER_LEN    32
#define AIC_SC_REG_AIC_TAG_VER_OFFSET 0

#define AIC_SC_REG_ISA_VER_LEN     16
#define AIC_SC_REG_ISA_VER_OFFSET  16
#define AIC_SC_REG_CORE_VER_LEN    16
#define AIC_SC_REG_CORE_VER_OFFSET 0

#define AIC_SC_REG_SMMU_SVN_VER_0_LEN    32
#define AIC_SC_REG_SMMU_SVN_VER_0_OFFSET 0

#define AIC_SC_REG_SMMU_SVN_VER_1_LEN    32
#define AIC_SC_REG_SMMU_SVN_VER_1_OFFSET 0

#define AIC_SC_REG_DISPATCH_SVN_VER_0_LEN    32
#define AIC_SC_REG_DISPATCH_SVN_VER_0_OFFSET 0

#define AIC_SC_REG_DISPATCH_SVN_VER_1_LEN    32
#define AIC_SC_REG_DISPATCH_SVN_VER_1_OFFSET 0

#define AIC_SC_REG_AA_SVN_VER_0_LEN    32
#define AIC_SC_REG_AA_SVN_VER_0_OFFSET 0

#define AIC_SC_REG_AA_SVN_VER_1_LEN    32
#define AIC_SC_REG_AA_SVN_VER_1_OFFSET 0

#define AIC_SC_REG_CRG_SVN_VER_0_LEN    32
#define AIC_SC_REG_CRG_SVN_VER_0_OFFSET 0

#define AIC_SC_REG_CRG_SVN_VER_1_LEN    32
#define AIC_SC_REG_CRG_SVN_VER_1_OFFSET 0

#define AIC_SC_REG_AIC_MEM_POWER_MODE_LEN     6
#define AIC_SC_REG_AIC_MEM_POWER_MODE_OFFSET  8
#define AIC_SC_REG_SMMU_MEM_POWER_MODE_LEN    6
#define AIC_SC_REG_SMMU_MEM_POWER_MODE_OFFSET 0

#define AIC_SC_REG_PUDELAY_AIC_LEN    1
#define AIC_SC_REG_PUDELAY_AIC_OFFSET 31
#define AIC_SC_REG_SD_MODE_LEN        1
#define AIC_SC_REG_SD_MODE_OFFSET     30

#define AIC_SC_REG_SMMU_SP_RAM_TMOD_LEN    10
#define AIC_SC_REG_SMMU_SP_RAM_TMOD_OFFSET 16
#define AIC_SC_REG_SMMU_TP_RAM_TMOD_LEN    10
#define AIC_SC_REG_SMMU_TP_RAM_TMOD_OFFSET 0

#define AIC_SC_REG_AIC_SP_RAM_TMOD_LEN    10
#define AIC_SC_REG_AIC_SP_RAM_TMOD_OFFSET 16
#define AIC_SC_REG_AIC_TP_RAM_TMOD_LEN    10
#define AIC_SC_REG_AIC_TP_RAM_TMOD_OFFSET 0

#define AIC_SC_REG_MTE_GDMA_ILLEGAL_BURST_NUM_LEN    1
#define AIC_SC_REG_MTE_GDMA_ILLEGAL_BURST_NUM_OFFSET 31
#define AIC_SC_REG_MTE_GDMA_ILLEGAL_BURST_LEN_LEN    1
#define AIC_SC_REG_MTE_GDMA_ILLEGAL_BURST_LEN_OFFSET 30
#define AIC_SC_REG_MTE_FPOS_LARGER_FSIZE_LEN         1
#define AIC_SC_REG_MTE_FPOS_LARGER_FSIZE_OFFSET      29
#define AIC_SC_REG_MTE_FMAPWH_LARGER_L1SIZE_LEN      1
#define AIC_SC_REG_MTE_FMAPWH_LARGER_L1SIZE_OFFSET   28
#define AIC_SC_REG_MTE_FMAP_LESS_KERNEL_LEN          1
#define AIC_SC_REG_MTE_FMAP_LESS_KERNEL_OFFSET       27
#define AIC_SC_REG_MTE_F1WPOS_LARGER_FSIZE_LEN       1
#define AIC_SC_REG_MTE_F1WPOS_LARGER_FSIZE_OFFSET    26
#define AIC_SC_REG_MTE_DECOMP_LEN                    1
#define AIC_SC_REG_MTE_DECOMP_OFFSET                 25
#define AIC_SC_REG_MTE_CIDX_OVERFLOW_LEN             1
#define AIC_SC_REG_MTE_CIDX_OVERFLOW_OFFSET          24
#define AIC_SC_REG_MTE_BIU_RDWR_RESP_LEN             1
#define AIC_SC_REG_MTE_BIU_RDWR_RESP_OFFSET          23
#define AIC_SC_REG_MTE_BAS_RADDR_OBOUND_LEN          1
#define AIC_SC_REG_MTE_BAS_RADDR_OBOUND_OFFSET       22
#define AIC_SC_REG_MTE_AIPP_ILLEGAL_PARAM_LEN        1
#define AIC_SC_REG_MTE_AIPP_ILLEGAL_PARAM_OFFSET     21
#define AIC_SC_REG_IFU_BUS_ERR_LEN                   1
#define AIC_SC_REG_IFU_BUS_ERR_OFFSET                20
#define AIC_SC_REG_CUBE_L0C_WRAP_AROUND_LEN          1
#define AIC_SC_REG_CUBE_L0C_WRAP_AROUND_OFFSET       19
#define AIC_SC_REG_CUBE_L0C_SELF_RDWR_CFLT_LEN       1
#define AIC_SC_REG_CUBE_L0C_SELF_RDWR_CFLT_OFFSET    18
#define AIC_SC_REG_CUBE_L0C_RDWR_CFLT_LEN            1
#define AIC_SC_REG_CUBE_L0C_RDWR_CFLT_OFFSET         17
#define AIC_SC_REG_CUBE_L0C_ECC_LEN                  1
#define AIC_SC_REG_CUBE_L0C_ECC_OFFSET               16
#define AIC_SC_REG_CUBE_L0B_WRAP_AROUND_LEN          1
#define AIC_SC_REG_CUBE_L0B_WRAP_AROUND_OFFSET       15
#define AIC_SC_REG_CUBE_L0B_RDWR_CFLT_LEN            1
#define AIC_SC_REG_CUBE_L0B_RDWR_CFLT_OFFSET         14
#define AIC_SC_REG_CUBE_L0B_ECC_LEN                  1
#define AIC_SC_REG_CUBE_L0B_ECC_OFFSET               13
#define AIC_SC_REG_CUBE_L0A_WRAP_AROUND_LEN          1
#define AIC_SC_REG_CUBE_L0A_WRAP_AROUND_OFFSET       12
#define AIC_SC_REG_CUBE_L0A_RDWR_CFLT_LEN            1
#define AIC_SC_REG_CUBE_L0A_RDWR_CFLT_OFFSET         11
#define AIC_SC_REG_CUBE_L0A_ECC_LEN                  1
#define AIC_SC_REG_CUBE_L0A_ECC_OFFSET               10
#define AIC_SC_REG_CUBE_INVLD_INPUT_LEN              1
#define AIC_SC_REG_CUBE_INVLD_INPUT_OFFSET           9
#define AIC_SC_REG_CCU_UB_ECC_LEN                    1
#define AIC_SC_REG_CCU_UB_ECC_OFFSET                 8
#define AIC_SC_REG_CCU_NEG_SQRT_LEN                  1
#define AIC_SC_REG_CCU_NEG_SQRT_OFFSET               7
#define AIC_SC_REG_CCU_LOOP_ERR_LEN                  1
#define AIC_SC_REG_CCU_LOOP_ERR_OFFSET               6
#define AIC_SC_REG_CCU_LOOP_CNT_ERR_LEN              1
#define AIC_SC_REG_CCU_LOOP_CNT_ERR_OFFSET           5
#define AIC_SC_REG_CCU_ILLEGAL_INSTR_LEN             1
#define AIC_SC_REG_CCU_ILLEGAL_INSTR_OFFSET          4
#define AIC_SC_REG_CCU_DIV0_LEN                      1
#define AIC_SC_REG_CCU_DIV0_OFFSET                   3
#define AIC_SC_REG_CCU_CALL_DEPTH_OVRFLW_LEN         1
#define AIC_SC_REG_CCU_CALL_DEPTH_OVRFLW_OFFSET      2
#define AIC_SC_REG_BIU_L2_WRITE_OOB_LEN              1
#define AIC_SC_REG_BIU_L2_WRITE_OOB_OFFSET           1
#define AIC_SC_REG_BIU_L2_READ_OOB_LEN               1
#define AIC_SC_REG_BIU_L2_READ_OOB_OFFSET            0

#define AIC_SC_REG_BIU_DFX_ERR_LEN                1
#define AIC_SC_REG_BIU_DFX_ERR_OFFSET             31
#define AIC_SC_REG_VEC_UB_WRAP_AROUND_LEN         1
#define AIC_SC_REG_VEC_UB_WRAP_AROUND_OFFSET      30
#define AIC_SC_REG_VEC_UB_SELF_RDWR_CFLT_LEN      1
#define AIC_SC_REG_VEC_UB_SELF_RDWR_CFLT_OFFSET   29
#define AIC_SC_REG_VEC_UB_ECC_LEN                 1
#define AIC_SC_REG_VEC_UB_ECC_OFFSET              28
#define AIC_SC_REG_VEC_SAME_BLK_ADDR_LEN          1
#define AIC_SC_REG_VEC_SAME_BLK_ADDR_OFFSET       27
#define AIC_SC_REG_VEC_NEG_SQRT_LEN               1
#define AIC_SC_REG_VEC_NEG_SQRT_OFFSET            26
#define AIC_SC_REG_VEC_NEG_LN_LEN                 1
#define AIC_SC_REG_VEC_NEG_LN_OFFSET              25
#define AIC_SC_REG_VEC_L0C_RDWR_CFLT_LEN          1
#define AIC_SC_REG_VEC_L0C_RDWR_CFLT_OFFSET       24
#define AIC_SC_REG_VEC_L0C_ECC_LEN                1
#define AIC_SC_REG_VEC_L0C_ECC_OFFSET             23
#define AIC_SC_REG_VEC_INF_NAN_LEN                1
#define AIC_SC_REG_VEC_INF_NAN_OFFSET             22
#define AIC_SC_REG_VEC_ILLEGAL_MASK_LEN           1
#define AIC_SC_REG_VEC_ILLEGAL_MASK_OFFSET        21
#define AIC_SC_REG_VEC_DIV0_LEN                   1
#define AIC_SC_REG_VEC_DIV0_OFFSET                20
#define AIC_SC_REG_VEC_DATA_EXCP_VEC_LEN          1
#define AIC_SC_REG_VEC_DATA_EXCP_VEC_OFFSET       19
#define AIC_SC_REG_VEC_DATA_EXCP_MTE_LEN          1
#define AIC_SC_REG_VEC_DATA_EXCP_MTE_OFFSET       18
#define AIC_SC_REG_VEC_DATA_EXCP_CCU_LEN          1
#define AIC_SC_REG_VEC_DATA_EXCP_CCU_OFFSET       17
#define AIC_SC_REG_MTE_WRITE_OVERFLOW_LEN         1
#define AIC_SC_REG_MTE_WRITE_OVERFLOW_OFFSET      16
#define AIC_SC_REG_MTE_WRITE_3D_OVERFLOW_LEN      1
#define AIC_SC_REG_MTE_WRITE_3D_OVERFLOW_OFFSET   15
#define AIC_SC_REG_MTE_UNZIP_LEN                  1
#define AIC_SC_REG_MTE_UNZIP_OFFSET               14
#define AIC_SC_REG_MTE_UB_ECC_LEN                 1
#define AIC_SC_REG_MTE_UB_ECC_OFFSET              13
#define AIC_SC_REG_MTE_TLU_ECC_LEN                1
#define AIC_SC_REG_MTE_TLU_ECC_OFFSET             12
#define AIC_SC_REG_MTE_ROB_ECC_LEN                1
#define AIC_SC_REG_MTE_ROB_ECC_OFFSET             11
#define AIC_SC_REG_MTE_READ_OVERFLOW_LEN          1
#define AIC_SC_REG_MTE_READ_OVERFLOW_OFFSET       10
#define AIC_SC_REG_MTE_PADDING_CFG_LEN            1
#define AIC_SC_REG_MTE_PADDING_CFG_OFFSET         9
#define AIC_SC_REG_MTE_L1_ECC_LEN                 1
#define AIC_SC_REG_MTE_L1_ECC_OFFSET              8
#define AIC_SC_REG_MTE_L0B_RDWR_CFLT_LEN          1
#define AIC_SC_REG_MTE_L0B_RDWR_CFLT_OFFSET       7
#define AIC_SC_REG_MTE_L0A_RDWR_CFLT_LEN          1
#define AIC_SC_REG_MTE_L0A_RDWR_CFLT_OFFSET       6
#define AIC_SC_REG_MTE_ILLEGAL_STRIDE_LEN         1
#define AIC_SC_REG_MTE_ILLEGAL_STRIDE_OFFSET      5
#define AIC_SC_REG_MTE_ILLEGAL_L1_3D_SIZE_LEN     1
#define AIC_SC_REG_MTE_ILLEGAL_L1_3D_SIZE_OFFSET  4
#define AIC_SC_REG_MTE_ILLEGAL_FM_SIZE_LEN        1
#define AIC_SC_REG_MTE_ILLEGAL_FM_SIZE_OFFSET     3
#define AIC_SC_REG_MTE_COMP_LEN                   1
#define AIC_SC_REG_MTE_COMP_OFFSET                2
#define AIC_SC_REG_MTE_GDMA_WRITE_OVERFLOW_LEN    1
#define AIC_SC_REG_MTE_GDMA_WRITE_OVERFLOW_OFFSET 1
#define AIC_SC_REG_MTE_GDMA_READ_OVERFLOW_LEN     1
#define AIC_SC_REG_MTE_GDMA_READ_OVERFLOW_OFFSET  0

#define AIC_SC_REG_MTE_GDMA_ILLEGAL_BURST_NUM_MASK_LEN    1
#define AIC_SC_REG_MTE_GDMA_ILLEGAL_BURST_NUM_MASK_OFFSET 31
#define AIC_SC_REG_MTE_GDMA_ILLEGAL_BURST_LEN_MASK_LEN    1
#define AIC_SC_REG_MTE_GDMA_ILLEGAL_BURST_LEN_MASK_OFFSET 30
#define AIC_SC_REG_MTE_FPOS_LARGER_FSIZE_MASK_LEN         1
#define AIC_SC_REG_MTE_FPOS_LARGER_FSIZE_MASK_OFFSET      29
#define AIC_SC_REG_MTE_FMAPWH_LARGER_L1SIZE_MASK_LEN      1
#define AIC_SC_REG_MTE_FMAPWH_LARGER_L1SIZE_MASK_OFFSET   28
#define AIC_SC_REG_MTE_FMAP_LESS_KERNEL_MASK_LEN          1
#define AIC_SC_REG_MTE_FMAP_LESS_KERNEL_MASK_OFFSET       27
#define AIC_SC_REG_MTE_F1WPOS_LARGER_FSIZE_MASK_LEN       1
#define AIC_SC_REG_MTE_F1WPOS_LARGER_FSIZE_MASK_OFFSET    26
#define AIC_SC_REG_MTE_DECOMP_MASK_LEN                    1
#define AIC_SC_REG_MTE_DECOMP_MASK_OFFSET                 25
#define AIC_SC_REG_MTE_CIDX_OVERFLOW_MASK_LEN             1
#define AIC_SC_REG_MTE_CIDX_OVERFLOW_MASK_OFFSET          24
#define AIC_SC_REG_MTE_BIU_RDWR_RESP_MASK_LEN             1
#define AIC_SC_REG_MTE_BIU_RDWR_RESP_MASK_OFFSET          23
#define AIC_SC_REG_MTE_BAS_RADDR_OBOUND_MASK_LEN          1
#define AIC_SC_REG_MTE_BAS_RADDR_OBOUND_MASK_OFFSET       22
#define AIC_SC_REG_MTE_AIPP_ILLEGAL_PARAM_MASK_LEN        1
#define AIC_SC_REG_MTE_AIPP_ILLEGAL_PARAM_MASK_OFFSET     21
#define AIC_SC_REG_IFU_BUS_ERR_MASK_LEN                   1
#define AIC_SC_REG_IFU_BUS_ERR_MASK_OFFSET                20
#define AIC_SC_REG_CUBE_L0C_WRAP_AROUND_MASK_LEN          1
#define AIC_SC_REG_CUBE_L0C_WRAP_AROUND_MASK_OFFSET       19
#define AIC_SC_REG_CUBE_L0C_SELF_RDWR_CFLT_MASK_LEN       1
#define AIC_SC_REG_CUBE_L0C_SELF_RDWR_CFLT_MASK_OFFSET    18
#define AIC_SC_REG_CUBE_L0C_RDWR_CFLT_MASK_LEN            1
#define AIC_SC_REG_CUBE_L0C_RDWR_CFLT_MASK_OFFSET         17
#define AIC_SC_REG_CUBE_L0C_ECC_MASK_LEN                  1
#define AIC_SC_REG_CUBE_L0C_ECC_MASK_OFFSET               16
#define AIC_SC_REG_CUBE_L0B_WRAP_AROUND_MASK_LEN          1
#define AIC_SC_REG_CUBE_L0B_WRAP_AROUND_MASK_OFFSET       15
#define AIC_SC_REG_CUBE_L0B_RDWR_CFLT_MASK_LEN            1
#define AIC_SC_REG_CUBE_L0B_RDWR_CFLT_MASK_OFFSET         14
#define AIC_SC_REG_CUBE_L0B_ECC_MASK_LEN                  1
#define AIC_SC_REG_CUBE_L0B_ECC_MASK_OFFSET               13
#define AIC_SC_REG_CUBE_L0A_WRAP_AROUND_MASK_LEN          1
#define AIC_SC_REG_CUBE_L0A_WRAP_AROUND_MASK_OFFSET       12
#define AIC_SC_REG_CUBE_L0A_RDWR_CFLT_MASK_LEN            1
#define AIC_SC_REG_CUBE_L0A_RDWR_CFLT_MASK_OFFSET         11
#define AIC_SC_REG_CUBE_L0A_ECC_MASK_LEN                  1
#define AIC_SC_REG_CUBE_L0A_ECC_MASK_OFFSET               10
#define AIC_SC_REG_CUBE_INVLD_INPUT_MASK_LEN              1
#define AIC_SC_REG_CUBE_INVLD_INPUT_MASK_OFFSET           9
#define AIC_SC_REG_CCU_UB_ECC_MASK_LEN                    1
#define AIC_SC_REG_CCU_UB_ECC_MASK_OFFSET                 8
#define AIC_SC_REG_CCU_NEG_SQRT_MASK_LEN                  1
#define AIC_SC_REG_CCU_NEG_SQRT_MASK_OFFSET               7
#define AIC_SC_REG_CCU_LOOP_ERR_MASK_LEN                  1
#define AIC_SC_REG_CCU_LOOP_ERR_MASK_OFFSET               6
#define AIC_SC_REG_CCU_LOOP_CNT_ERR_MASK_LEN              1
#define AIC_SC_REG_CCU_LOOP_CNT_ERR_MASK_OFFSET           5
#define AIC_SC_REG_CCU_ILLEGAL_INSTR_MASK_LEN             1
#define AIC_SC_REG_CCU_ILLEGAL_INSTR_MASK_OFFSET          4
#define AIC_SC_REG_CCU_DIV0_MASK_LEN                      1
#define AIC_SC_REG_CCU_DIV0_MASK_OFFSET                   3
#define AIC_SC_REG_CCU_CALL_DEPTH_OVRFLW_MASK_LEN         1
#define AIC_SC_REG_CCU_CALL_DEPTH_OVRFLW_MASK_OFFSET      2
#define AIC_SC_REG_BIU_L2_WRITE_OOB_MASK_LEN              1
#define AIC_SC_REG_BIU_L2_WRITE_OOB_MASK_OFFSET           1
#define AIC_SC_REG_BIU_L2_READ_OOB_MASK_LEN               1
#define AIC_SC_REG_BIU_L2_READ_OOB_MASK_OFFSET            0

#define AIC_SC_REG_BIU_DFX_ERR_MASK_LEN                1
#define AIC_SC_REG_BIU_DFX_ERR_MASK_OFFSET             31
#define AIC_SC_REG_VEC_UB_WRAP_AROUND_MASK_LEN         1
#define AIC_SC_REG_VEC_UB_WRAP_AROUND_MASK_OFFSET      30
#define AIC_SC_REG_VEC_UB_SELF_RDWR_CFLT_MASK_LEN      1
#define AIC_SC_REG_VEC_UB_SELF_RDWR_CFLT_MASK_OFFSET   29
#define AIC_SC_REG_VEC_UB_ECC_MASK_LEN                 1
#define AIC_SC_REG_VEC_UB_ECC_MASK_OFFSET              28
#define AIC_SC_REG_VEC_SAME_BLK_ADDR_MASK_LEN          1
#define AIC_SC_REG_VEC_SAME_BLK_ADDR_MASK_OFFSET       27
#define AIC_SC_REG_VEC_NEG_SQRT_MASK_LEN               1
#define AIC_SC_REG_VEC_NEG_SQRT_MASK_OFFSET            26
#define AIC_SC_REG_VEC_NEG_LN_MASK_LEN                 1
#define AIC_SC_REG_VEC_NEG_LN_MASK_OFFSET              25
#define AIC_SC_REG_VEC_L0C_RDWR_CFLT_MASK_LEN          1
#define AIC_SC_REG_VEC_L0C_RDWR_CFLT_MASK_OFFSET       24
#define AIC_SC_REG_VEC_L0C_ECC_MASK_LEN                1
#define AIC_SC_REG_VEC_L0C_ECC_MASK_OFFSET             23
#define AIC_SC_REG_VEC_INF_NAN_MASK_LEN                1
#define AIC_SC_REG_VEC_INF_NAN_MASK_OFFSET             22
#define AIC_SC_REG_VEC_ILLEGAL_MASK_MASK_LEN           1
#define AIC_SC_REG_VEC_ILLEGAL_MASK_MASK_OFFSET        21
#define AIC_SC_REG_VEC_DIV0_MASK_LEN                   1
#define AIC_SC_REG_VEC_DIV0_MASK_OFFSET                20
#define AIC_SC_REG_VEC_DATA_EXCP_VEC_MASK_LEN          1
#define AIC_SC_REG_VEC_DATA_EXCP_VEC_MASK_OFFSET       19
#define AIC_SC_REG_VEC_DATA_EXCP_MTE_MASK_LEN          1
#define AIC_SC_REG_VEC_DATA_EXCP_MTE_MASK_OFFSET       18
#define AIC_SC_REG_VEC_DATA_EXCP_CCU_MASK_LEN          1
#define AIC_SC_REG_VEC_DATA_EXCP_CCU_MASK_OFFSET       17
#define AIC_SC_REG_MTE_WRITE_OVERFLOW_MASK_LEN         1
#define AIC_SC_REG_MTE_WRITE_OVERFLOW_MASK_OFFSET      16
#define AIC_SC_REG_MTE_WRITE_3D_OVERFLOW_MASK_LEN      1
#define AIC_SC_REG_MTE_WRITE_3D_OVERFLOW_MASK_OFFSET   15
#define AIC_SC_REG_MTE_UNZIP_MASK_LEN                  1
#define AIC_SC_REG_MTE_UNZIP_MASK_OFFSET               14
#define AIC_SC_REG_MTE_UB_ECC_MASK_LEN                 1
#define AIC_SC_REG_MTE_UB_ECC_MASK_OFFSET              13
#define AIC_SC_REG_MTE_TLU_ECC_MASK_LEN                1
#define AIC_SC_REG_MTE_TLU_ECC_MASK_OFFSET             12
#define AIC_SC_REG_MTE_ROB_ECC_MASK_LEN                1
#define AIC_SC_REG_MTE_ROB_ECC_MASK_OFFSET             11
#define AIC_SC_REG_MTE_READ_OVERFLOW_MASK_LEN          1
#define AIC_SC_REG_MTE_READ_OVERFLOW_MASK_OFFSET       10
#define AIC_SC_REG_MTE_PADDING_CFG_MASK_LEN            1
#define AIC_SC_REG_MTE_PADDING_CFG_MASK_OFFSET         9
#define AIC_SC_REG_MTE_L1_ECC_MASK_LEN                 1
#define AIC_SC_REG_MTE_L1_ECC_MASK_OFFSET              8
#define AIC_SC_REG_MTE_L0B_RDWR_CFLT_MASK_LEN          1
#define AIC_SC_REG_MTE_L0B_RDWR_CFLT_MASK_OFFSET       7
#define AIC_SC_REG_MTE_L0A_RDWR_CFLT_MASK_LEN          1
#define AIC_SC_REG_MTE_L0A_RDWR_CFLT_MASK_OFFSET       6
#define AIC_SC_REG_MTE_ILLEGAL_STRIDE_MASK_LEN         1
#define AIC_SC_REG_MTE_ILLEGAL_STRIDE_MASK_OFFSET      5
#define AIC_SC_REG_MTE_ILLEGAL_L1_3D_SIZE_MASK_LEN     1
#define AIC_SC_REG_MTE_ILLEGAL_L1_3D_SIZE_MASK_OFFSET  4
#define AIC_SC_REG_MTE_ILLEGAL_FM_SIZE_MASK_LEN        1
#define AIC_SC_REG_MTE_ILLEGAL_FM_SIZE_MASK_OFFSET     3
#define AIC_SC_REG_MTE_COMP_MASK_LEN                   1
#define AIC_SC_REG_MTE_COMP_MASK_OFFSET                2
#define AIC_SC_REG_MTE_GDMA_WRITE_OVERFLOW_MASK_LEN    1
#define AIC_SC_REG_MTE_GDMA_WRITE_OVERFLOW_MASK_OFFSET 1
#define AIC_SC_REG_MTE_GDMA_READ_OVERFLOW_MASK_LEN     1
#define AIC_SC_REG_MTE_GDMA_READ_OVERFLOW_MASK_OFFSET  0

#define AIC_SC_REG_BIU_ERR_ADDR_0_LEN    32
#define AIC_SC_REG_BIU_ERR_ADDR_0_OFFSET 0

#define AIC_SC_REG_BIU_ERR_ADDR_1_LEN    32
#define AIC_SC_REG_BIU_ERR_ADDR_1_OFFSET 0

#define AIC_SC_REG_CCU_ERR_PC_1_LEN    8
#define AIC_SC_REG_CCU_ERR_PC_1_OFFSET 23
#define AIC_SC_REG_CCU_ERR_ADDR_LEN    15
#define AIC_SC_REG_CCU_ERR_ADDR_OFFSET 8
#define AIC_SC_REG_CCU_ERR_PC_0_LEN    8
#define AIC_SC_REG_CCU_ERR_PC_0_OFFSET 0

#define AIC_SC_REG_CCU_ERR_INSTR_LEN    32
#define AIC_SC_REG_CCU_ERR_INSTR_OFFSET 0

#define AIC_SC_REG_CUBE_ERR_PC_1_LEN    8
#define AIC_SC_REG_CUBE_ERR_PC_1_OFFSET 24
#define AIC_SC_REG_CUBE_ERR_ADDR_LEN    16
#define AIC_SC_REG_CUBE_ERR_ADDR_OFFSET 8
#define AIC_SC_REG_CUBE_ERR_PC_0_LEN    8
#define AIC_SC_REG_CUBE_ERR_PC_0_OFFSET 0

#define AIC_SC_REG_BIU_UNSPLIT_ERR_INFO_LEN    3
#define AIC_SC_REG_BIU_UNSPLIT_ERR_INFO_OFFSET 0

#define AIC_SC_REG_IFU_ERR_ADDR_0_LEN    30
#define AIC_SC_REG_IFU_ERR_ADDR_0_OFFSET 2

#define AIC_SC_REG_IFU_ERR_TYPE_LEN      4
#define AIC_SC_REG_IFU_ERR_TYPE_OFFSET   16
#define AIC_SC_REG_IFU_ERR_ADDR_1_LEN    16
#define AIC_SC_REG_IFU_ERR_ADDR_1_OFFSET 0

#define AIC_SC_REG_MTE_ERR_TYPE_LEN    8
#define AIC_SC_REG_MTE_ERR_TYPE_OFFSET 24
#define AIC_SC_REG_MTE_ERR_ADDR_LEN    16
#define AIC_SC_REG_MTE_ERR_ADDR_OFFSET 8
#define AIC_SC_REG_MTE_ERR_PC_0_LEN    8
#define AIC_SC_REG_MTE_ERR_PC_0_OFFSET 0

#define AIC_SC_REG_MTE_ERR_PC_1_LEN    8
#define AIC_SC_REG_MTE_ERR_PC_1_OFFSET 0

#define AIC_SC_REG_VEC_ERR_ADDR_LEN    13
#define AIC_SC_REG_VEC_ERR_ADDR_OFFSET 16
#define AIC_SC_REG_VEC_ERR_RCNT_LEN    8
#define AIC_SC_REG_VEC_ERR_RCNT_OFFSET 8
#define AIC_SC_REG_VEC_ERR_PC_0_LEN    8
#define AIC_SC_REG_VEC_ERR_PC_0_OFFSET 0

#define AIC_SC_REG_VEC_ERR_PC_1_LEN    8
#define AIC_SC_REG_VEC_ERR_PC_1_OFFSET 0

#define AIC_SC_REG_MTE_WARN_ROB_ECC_1BIT_ADDR_LEN    11
#define AIC_SC_REG_MTE_WARN_ROB_ECC_1BIT_ADDR_OFFSET 16
#define AIC_SC_REG_MTE_WARN_L1_ECC_1BIT_ADDR_LEN     15
#define AIC_SC_REG_MTE_WARN_L1_ECC_1BIT_ADDR_OFFSET  0

#define AIC_SC_REG_CCU_WARN_VECIQ_ECC_1BIT_ADDR_LEN    7
#define AIC_SC_REG_CCU_WARN_VECIQ_ECC_1BIT_ADDR_OFFSET 23
#define AIC_SC_REG_CCU_WARN_SBUF_ECC_1BIT_ADDR_LEN     11
#define AIC_SC_REG_CCU_WARN_SBUF_ECC_1BIT_ADDR_OFFSET  7
#define AIC_SC_REG_MTE_WARN_TLU_ECC_1BIT_ADDR_LEN      7
#define AIC_SC_REG_MTE_WARN_TLU_ECC_1BIT_ADDR_OFFSET   0

#define AIC_SC_REG_VEC_WARN_L0C_ECC_1BIT_ADDR_LEN    10
#define AIC_SC_REG_VEC_WARN_L0C_ECC_1BIT_ADDR_OFFSET 16
#define AIC_SC_REG_VEC_WARN_UB_ECC_1BIT_ADDR_LEN     13
#define AIC_SC_REG_VEC_WARN_UB_ECC_1BIT_ADDR_OFFSET  0

#define AIC_SC_REG_CUBE_WARN_L0C_ECC_1BIT_ADDR_LEN      16
#define AIC_SC_REG_CUBE_WARN_L0C_ECC_1BIT_ADDR_OFFSET   16
#define AIC_SC_REG_CUBE_WARN_L0B_ECC_1BIT_ADDR_L_LEN    7
#define AIC_SC_REG_CUBE_WARN_L0B_ECC_1BIT_ADDR_L_OFFSET 7
#define AIC_SC_REG_CUBE_WARN_L0A_ECC_1BIT_ADDR_L_LEN    7
#define AIC_SC_REG_CUBE_WARN_L0A_ECC_1BIT_ADDR_L_OFFSET 0

#define AIC_SC_REG_CUBE_L0C_ECC_FORCE_LEN    1
#define AIC_SC_REG_CUBE_L0C_ECC_FORCE_OFFSET 16
#define AIC_SC_REG_CUBE_L0B_ECC_FORCE_LEN    1
#define AIC_SC_REG_CUBE_L0B_ECC_FORCE_OFFSET 13
#define AIC_SC_REG_CUBE_L0A_ECC_FORCE_LEN    1
#define AIC_SC_REG_CUBE_L0A_ECC_FORCE_OFFSET 10
#define AIC_SC_REG_CCU_UB_ECC_FORCE_LEN      1
#define AIC_SC_REG_CCU_UB_ECC_FORCE_OFFSET   8

#define AIC_SC_REG_VEC_UB_ECC_FORCE_LEN           1
#define AIC_SC_REG_VEC_UB_ECC_FORCE_OFFSET        26
#define AIC_SC_REG_VEC_L0C_ECC_FORCE_LEN          1
#define AIC_SC_REG_VEC_L0C_ECC_FORCE_OFFSET       21
#define AIC_SC_REG_MTE_AIPP_ECC_FORCE_LEN         1
#define AIC_SC_REG_MTE_AIPP_ECC_FORCE_OFFSET      15
#define AIC_SC_REG_MTE_STB_ECC_FORCE_LEN          1
#define AIC_SC_REG_MTE_STB_ECC_FORCE_OFFSET       14
#define AIC_SC_REG_MTE_ERR_CACHE_ECC_FORCE_LEN    1
#define AIC_SC_REG_MTE_ERR_CACHE_ECC_FORCE_OFFSET 13
#define AIC_SC_REG_MTE_UB_ECC_FORCE_LEN           1
#define AIC_SC_REG_MTE_UB_ECC_FORCE_OFFSET        12
#define AIC_SC_REG_MTE_TLU_ECC_FORCE_LEN          1
#define AIC_SC_REG_MTE_TLU_ECC_FORCE_OFFSET       11
#define AIC_SC_REG_MTE_ROB_ECC_FORCE_LEN          1
#define AIC_SC_REG_MTE_ROB_ECC_FORCE_OFFSET       10
#define AIC_SC_REG_MTE_L1_ECC_FORCE_LEN           1
#define AIC_SC_REG_MTE_L1_ECC_FORCE_OFFSET        7
#define AIC_SC_REG_VEC_UB_ECC_MBERR_FORCE_LEN     1
#define AIC_SC_REG_VEC_UB_ECC_MBERR_FORCE_OFFSET  2
#define AIC_SC_REG_VEC_IC_ECC_ERR_FORCE_LEN       1
#define AIC_SC_REG_VEC_IC_ECC_ERR_FORCE_OFFSET    1
#define AIC_SC_REG_VEC_PB_ECC_MBERR_FORCE_LEN     1
#define AIC_SC_REG_VEC_PB_ECC_MBERR_FORCE_OFFSET  0

#define AIC_SC_REG_FIXP_L0C_ECC_FORCE_LEN       1
#define AIC_SC_REG_FIXP_L0C_ECC_FORCE_OFFSET    5
#define AIC_SC_REG_CCU_PB_ECC_FORCE_LEN         1
#define AIC_SC_REG_CCU_PB_ECC_FORCE_OFFSET      4
#define AIC_SC_REG_CCU_DC_TAG_ECC_FORCE_LEN     1
#define AIC_SC_REG_CCU_DC_TAG_ECC_FORCE_OFFSET  3
#define AIC_SC_REG_CCU_DC_DATA_ECC_FORCE_LEN    1
#define AIC_SC_REG_CCU_DC_DATA_ECC_FORCE_OFFSET 2
#define AIC_SC_REG_CCU_VECIQ_ECC_FORCE_LEN      1
#define AIC_SC_REG_CCU_VECIQ_ECC_FORCE_OFFSET   1
#define AIC_SC_REG_CCU_SBUF_ECC_FORCE_LEN       1
#define AIC_SC_REG_CCU_SBUF_ECC_FORCE_OFFSET    0

#define AIC_SC_REG_CCU_DC_DATA_ECC_LEN                    1
#define AIC_SC_REG_CCU_DC_DATA_ECC_OFFSET                 31
#define AIC_SC_REG_CCU_VECIQ_ECC_LEN                      1
#define AIC_SC_REG_CCU_VECIQ_ECC_OFFSET                   30
#define AIC_SC_REG_MTE_ERR_READ_3D_OVERFLOW_LEN           1
#define AIC_SC_REG_MTE_ERR_READ_3D_OVERFLOW_OFFSET        29
#define AIC_SC_REG_MTE_ERR_ILLEGAL_SMALLK_CFG_LEN         1
#define AIC_SC_REG_MTE_ERR_ILLEGAL_SMALLK_CFG_OFFSET      28
#define AIC_SC_REG_MTE_ERR_ILLEGAL_K_M_START_POS_LEN      1
#define AIC_SC_REG_MTE_ERR_ILLEGAL_K_M_START_POS_OFFSET   27
#define AIC_SC_REG_MTE_ERR_ILLEGAL_K_M_EXT_STEP_LEN       1
#define AIC_SC_REG_MTE_ERR_ILLEGAL_K_M_EXT_STEP_OFFSET    26
#define AIC_SC_REG_MTE_ERR_ILLEGAL_CHN_SIZE_LEN           1
#define AIC_SC_REG_MTE_ERR_ILLEGAL_CHN_SIZE_OFFSET        25
#define AIC_SC_REG_MTE_ERR_ILLEGAL_H_SIZE_LEN             1
#define AIC_SC_REG_MTE_ERR_ILLEGAL_H_SIZE_OFFSET          24
#define AIC_SC_REG_MTE_ERR_ILLEGAL_W_SIZE_LEN             1
#define AIC_SC_REG_MTE_ERR_ILLEGAL_W_SIZE_OFFSET          23
#define AIC_SC_REG_MTE_ERR_ILLEGAL_H_COV_PAD_CTL_LEN      1
#define AIC_SC_REG_MTE_ERR_ILLEGAL_H_COV_PAD_CTL_OFFSET   22
#define AIC_SC_REG_MTE_ERR_ILLEGAL_V_COV_PAD_CTL_LEN      1
#define AIC_SC_REG_MTE_ERR_ILLEGAL_V_COV_PAD_CTL_OFFSET   21
#define AIC_SC_REG_MTE_ERR_WINO_L0B_READ_OVERFLOW_LEN     1
#define AIC_SC_REG_MTE_ERR_WINO_L0B_READ_OVERFLOW_OFFSET  20
#define AIC_SC_REG_MTE_ERR_WINO_L0B_WRITE_OVERFLOW_LEN    1
#define AIC_SC_REG_MTE_ERR_WINO_L0B_WRITE_OVERFLOW_OFFSET 19
#define AIC_SC_REG_MTE_ERR_DW_FMAP_H_ILLEGAL_LEN          1
#define AIC_SC_REG_MTE_ERR_DW_FMAP_H_ILLEGAL_OFFSET       18
#define AIC_SC_REG_MTE_ERR_DW_PAD_CONF_ERR_LEN            1
#define AIC_SC_REG_MTE_ERR_DW_PAD_CONF_ERR_OFFSET         17
#define AIC_SC_REG_MTE_ERR_ADDR_MISALIGN_LEN              1
#define AIC_SC_REG_MTE_ERR_ADDR_MISALIGN_OFFSET           16
#define AIC_SC_REG_CCU_BUS_ERR_LEN                        1
#define AIC_SC_REG_CCU_BUS_ERR_OFFSET                     15
#define AIC_SC_REG_CCU_ADDR_ERR_LEN                       1
#define AIC_SC_REG_CCU_ADDR_ERR_OFFSET                    14
#define AIC_SC_REG_VEC_INSTR_UNDEF_LEN                    1
#define AIC_SC_REG_VEC_INSTR_UNDEF_OFFSET                 13
#define AIC_SC_REG_VEC_INSTR_ILLEGAL_CFG_LEN              1
#define AIC_SC_REG_VEC_INSTR_ILLEGAL_CFG_OFFSET           12
#define AIC_SC_REG_VEC_INSTR_ADDR_MISALIGN_LEN            1
#define AIC_SC_REG_VEC_INSTR_ADDR_MISALIGN_OFFSET         11
#define AIC_SC_REG_MTE_ATM_ADDR_MISALG_LEN                1
#define AIC_SC_REG_MTE_ATM_ADDR_MISALG_OFFSET             10
#define AIC_SC_REG_MTE_ILLEGAL_SCHN_CFG_LEN               1
#define AIC_SC_REG_MTE_ILLEGAL_SCHN_CFG_OFFSET            9
#define AIC_SC_REG_CCU_INF_NAN_LEN                        1
#define AIC_SC_REG_CCU_INF_NAN_OFFSET                     8
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_K_SIZE_LEN         1
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_K_SIZE_OFFSET      7
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_FETCH_POS_LEN      1
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_FETCH_POS_OFFSET   6
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_1ST_WIN_POS_LEN    1
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_1ST_WIN_POS_OFFSET 5
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_STRIDE_LEN         1
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_STRIDE_OFFSET      4
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_FM_SIZE_LEN        1
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_FM_SIZE_OFFSET     3
#define AIC_SC_REG_VEC_COL2IMG_RD_DFM_ADDR_OVFFLOW_LEN    1
#define AIC_SC_REG_VEC_COL2IMG_RD_DFM_ADDR_OVFFLOW_OFFSET 2
#define AIC_SC_REG_VEC_COL2IMG_RD_FM_ADDR_OVFLOW_LEN      1
#define AIC_SC_REG_VEC_COL2IMG_RD_FM_ADDR_OVFLOW_OFFSET   1
#define AIC_SC_REG_CCU_SBUF_ECC_LEN                       1
#define AIC_SC_REG_CCU_SBUF_ECC_OFFSET                    0

#define AIC_SC_REG_CCU_SAFETY_CRC_ERR_LEN           1
#define AIC_SC_REG_CCU_SAFETY_CRC_ERR_OFFSET        31
#define AIC_SC_REG_CUBE_ILLEGAL_INSTR_LEN           1
#define AIC_SC_REG_CUBE_ILLEGAL_INSTR_OFFSET        30
#define AIC_SC_REG_MTE_UB_RD_OVFLW_LEN              1
#define AIC_SC_REG_MTE_UB_RD_OVFLW_OFFSET           29
#define AIC_SC_REG_MTE_UB_WR_OVFLW_LEN              1
#define AIC_SC_REG_MTE_UB_WR_OVFLW_OFFSET           28
#define AIC_SC_REG_CCU_PB_ECC_ERR_LEN               1
#define AIC_SC_REG_CCU_PB_ECC_ERR_OFFSET            27
#define AIC_SC_REG_CCU_LSU_ERR_LEN                  1
#define AIC_SC_REG_CCU_LSU_ERR_OFFSET               26
#define AIC_SC_REG_CCU_MPU_ERR_LEN                  1
#define AIC_SC_REG_CCU_MPU_ERR_OFFSET               25
#define AIC_SC_REG_CCU_SEQ_ERR_LEN                  1
#define AIC_SC_REG_CCU_SEQ_ERR_OFFSET               24
#define AIC_SC_REG_MTE_ERR_WAIPP_LEN                1
#define AIC_SC_REG_MTE_ERR_WAIPP_OFFSET             23
#define AIC_SC_REG_MTE_ERR_HEBCE_LEN                1
#define AIC_SC_REG_MTE_ERR_HEBCE_OFFSET             22
#define AIC_SC_REG_MTE_ERR_HEBCD_LEN                1
#define AIC_SC_REG_MTE_ERR_HEBCD_OFFSET             21
#define AIC_SC_REG_MTE_ERR_INSTR_ILLEGAL_CFG_LEN    1
#define AIC_SC_REG_MTE_ERR_INSTR_ILLEGAL_CFG_OFFSET 20
#define AIC_SC_REG_CUBE_ERR_HSET_CNT_OVF_LEN        1
#define AIC_SC_REG_CUBE_ERR_HSET_CNT_OVF_OFFSET     19
#define AIC_SC_REG_CUBE_ERR_HSET_CNT_UNF_LEN        1
#define AIC_SC_REG_CUBE_ERR_HSET_CNT_UNF_OFFSET     18
#define AIC_SC_REG_MTE_ERR_CACHE_ECC_LEN            1
#define AIC_SC_REG_MTE_ERR_CACHE_ECC_OFFSET         17
#define AIC_SC_REG_CCU_ERR_PARITY_ERR_LEN           1
#define AIC_SC_REG_CCU_ERR_PARITY_ERR_OFFSET        16
#define AIC_SC_REG_MTE_ERR_WAITSET_LEN              1
#define AIC_SC_REG_MTE_ERR_WAITSET_OFFSET           15
#define AIC_SC_REG_MTE_ERR_FIFO_PARITY_LEN          1
#define AIC_SC_REG_MTE_ERR_FIFO_PARITY_OFFSET       14
#define AIC_SC_REG_SC_REG_PARITY_ERR_LEN            1
#define AIC_SC_REG_SC_REG_PARITY_ERR_OFFSET         13
#define AIC_SC_REG_FIXP_ERR_FBUF_READ_OVFLW_LEN     1
#define AIC_SC_REG_FIXP_ERR_FBUF_READ_OVFLW_OFFSET  12
#define AIC_SC_REG_FIXP_ERR_FBUF_WRITE_OVFLW_LEN    1
#define AIC_SC_REG_FIXP_ERR_FBUF_WRITE_OVFLW_OFFSET 11
#define AIC_SC_REG_FIXP_ERR_WRITE_UB_OVFLW_LEN      1
#define AIC_SC_REG_FIXP_ERR_WRITE_UB_OVFLW_OFFSET   10
#define AIC_SC_REG_FIXP_ERR_WRITE_L1_OVFLW_LEN      1
#define AIC_SC_REG_FIXP_ERR_WRITE_L1_OVFLW_OFFSET   9
#define AIC_SC_REG_FIXP_ERR_READ_UB_OVFLW_LEN       1
#define AIC_SC_REG_FIXP_ERR_READ_UB_OVFLW_OFFSET    8
#define AIC_SC_REG_FIXP_ERR_READ_L1_OVFLW_LEN       1
#define AIC_SC_REG_FIXP_ERR_READ_L1_OVFLW_OFFSET    7
#define AIC_SC_REG_FIXP_ERR_READ_L0C_OVFLW_LEN      1
#define AIC_SC_REG_FIXP_ERR_READ_L0C_OVFLW_OFFSET   6
#define AIC_SC_REG_FIXP_ERR_ILLEGAL_CFG_LEN         1
#define AIC_SC_REG_FIXP_ERR_ILLEGAL_CFG_OFFSET      5
#define AIC_SC_REG_FIXP_ERR_INSTR_ADDR_MISAL_LEN    1
#define AIC_SC_REG_FIXP_ERR_INSTR_ADDR_MISAL_OFFSET 4
#define AIC_SC_REG_CNT_SW_BUS_ERR_LEN               1
#define AIC_SC_REG_CNT_SW_BUS_ERR_OFFSET            3
#define AIC_SC_REG_CCU_NEG_SQRT_FP_LEN              1
#define AIC_SC_REG_CCU_NEG_SQRT_FP_OFFSET           2
#define AIC_SC_REG_CCU_DIV0_FP_LEN                  1
#define AIC_SC_REG_CCU_DIV0_FP_OFFSET               1
#define AIC_SC_REG_CCU_DC_TAG_ECC_LEN               1
#define AIC_SC_REG_CCU_DC_TAG_ECC_OFFSET            0

#define AIC_SC_REG_CCU_DC_DATA_ECC_MASK_LEN                    1
#define AIC_SC_REG_CCU_DC_DATA_ECC_MASK_OFFSET                 31
#define AIC_SC_REG_CCU_VECIQ_ECC_MASK_LEN                      1
#define AIC_SC_REG_CCU_VECIQ_ECC_MASK_OFFSET                   30
#define AIC_SC_REG_MTE_ERR_READ_3D_OVERFLOW_MASK_LEN           1
#define AIC_SC_REG_MTE_ERR_READ_3D_OVERFLOW_MASK_OFFSET        29
#define AIC_SC_REG_MTE_ERR_ILLEGAL_SMALLK_CFG_MASK_LEN         1
#define AIC_SC_REG_MTE_ERR_ILLEGAL_SMALLK_CFG_MASK_OFFSET      28
#define AIC_SC_REG_MTE_ERR_ILLEGAL_K_M_START_POS_MASK_LEN      1
#define AIC_SC_REG_MTE_ERR_ILLEGAL_K_M_START_POS_MASK_OFFSET   27
#define AIC_SC_REG_MTE_ERR_ILLEGAL_K_M_EXT_STEP_MASK_LEN       1
#define AIC_SC_REG_MTE_ERR_ILLEGAL_K_M_EXT_STEP_MASK_OFFSET    26
#define AIC_SC_REG_MTE_ERR_ILLEGAL_CHN_SIZE_MASK_LEN           1
#define AIC_SC_REG_MTE_ERR_ILLEGAL_CHN_SIZE_MASK_OFFSET        25
#define AIC_SC_REG_MTE_ERR_ILLEGAL_H_SIZE_MASK_LEN             1
#define AIC_SC_REG_MTE_ERR_ILLEGAL_H_SIZE_MASK_OFFSET          24
#define AIC_SC_REG_MTE_ERR_ILLEGAL_W_SIZE_MASK_LEN             1
#define AIC_SC_REG_MTE_ERR_ILLEGAL_W_SIZE_MASK_OFFSET          23
#define AIC_SC_REG_MTE_ERR_ILLEGAL_H_COV_PAD_CTL_MASK_LEN      1
#define AIC_SC_REG_MTE_ERR_ILLEGAL_H_COV_PAD_CTL_MASK_OFFSET   22
#define AIC_SC_REG_MTE_ERR_ILLEGAL_V_COV_PAD_CTL_MASK_LEN      1
#define AIC_SC_REG_MTE_ERR_ILLEGAL_V_COV_PAD_CTL_MASK_OFFSET   21
#define AIC_SC_REG_MTE_ERR_WINO_L0B_READ_OVERFLOW_MASK_LEN     1
#define AIC_SC_REG_MTE_ERR_WINO_L0B_READ_OVERFLOW_MASK_OFFSET  20
#define AIC_SC_REG_MTE_ERR_WINO_L0B_WRITE_OVERFLOW_MASK_LEN    1
#define AIC_SC_REG_MTE_ERR_WINO_L0B_WRITE_OVERFLOW_MASK_OFFSET 19
#define AIC_SC_REG_MTE_ERR_DW_FMAP_H_ILLEGAL_MASK_LEN          1
#define AIC_SC_REG_MTE_ERR_DW_FMAP_H_ILLEGAL_MASK_OFFSET       18
#define AIC_SC_REG_MTE_ERR_DW_PAD_CONF_ERR_MASK_LEN            1
#define AIC_SC_REG_MTE_ERR_DW_PAD_CONF_ERR_MASK_OFFSET         17
#define AIC_SC_REG_MTE_ERR_ADDR_MISALIGN_MASK_LEN              1
#define AIC_SC_REG_MTE_ERR_ADDR_MISALIGN_MASK_OFFSET           16
#define AIC_SC_REG_CCU_BUS_ERR_MASK_LEN                        1
#define AIC_SC_REG_CCU_BUS_ERR_MASK_OFFSET                     15
#define AIC_SC_REG_CCU_ADDR_ERR_MASK_LEN                       1
#define AIC_SC_REG_CCU_ADDR_ERR_MASK_OFFSET                    14
#define AIC_SC_REG_VEC_INSTR_UNDEF_MASK_LEN                    1
#define AIC_SC_REG_VEC_INSTR_UNDEF_MASK_OFFSET                 13
#define AIC_SC_REG_VEC_INSTR_ILLEGAL_CFG_MASK_LEN              1
#define AIC_SC_REG_VEC_INSTR_ILLEGAL_CFG_MASK_OFFSET           12
#define AIC_SC_REG_VEC_INSTR_ADDR_MISALIGN_MASK_LEN            1
#define AIC_SC_REG_VEC_INSTR_ADDR_MISALIGN_MASK_OFFSET         11
#define AIC_SC_REG_MTE_ATM_ADDR_MISALG_MASK_LEN                1
#define AIC_SC_REG_MTE_ATM_ADDR_MISALG_MASK_OFFSET             10
#define AIC_SC_REG_MTE_ILLEGAL_SCHN_CFG_MASK_LEN               1
#define AIC_SC_REG_MTE_ILLEGAL_SCHN_CFG_MASK_OFFSET            9
#define AIC_SC_REG_CCU_INF_NAN_MASK_LEN                        1
#define AIC_SC_REG_CCU_INF_NAN_MASK_OFFSET                     8
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_K_SIZE_MASK_LEN         1
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_K_SIZE_MASK_OFFSET      7
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_FETCH_POS_MASK_LEN      1
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_FETCH_POS_MASK_OFFSET   6
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_1ST_WIN_POS_MASK_LEN    1
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_1ST_WIN_POS_MASK_OFFSET 5
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_STRIDE_MASK_LEN         1
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_STRIDE_MASK_OFFSET      4
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_FM_SIZE_MASK_LEN        1
#define AIC_SC_REG_VEC_COL2IMG_ILLEGAL_FM_SIZE_MASK_OFFSET     3
#define AIC_SC_REG_VEC_COL2IMG_RD_DFM_ADDR_OVFFLOW_MASK_LEN    1
#define AIC_SC_REG_VEC_COL2IMG_RD_DFM_ADDR_OVFFLOW_MASK_OFFSET 2
#define AIC_SC_REG_VEC_COL2IMG_RD_FM_ADDR_OVFLOW_MASK_LEN      1
#define AIC_SC_REG_VEC_COL2IMG_RD_FM_ADDR_OVFLOW_MASK_OFFSET   1
#define AIC_SC_REG_CCU_SBUF_ECC_MASK_LEN                       1
#define AIC_SC_REG_CCU_SBUF_ECC_MASK_OFFSET                    0

#define AIC_SC_REG_CCU_SAFETY_CRC_ERR_MASK_LEN           1
#define AIC_SC_REG_CCU_SAFETY_CRC_ERR_MASK_OFFSET        31
#define AIC_SC_REG_CUBE_ILLEGAL_INSTR_MASK_LEN           1
#define AIC_SC_REG_CUBE_ILLEGAL_INSTR_MASK_OFFSET        30
#define AIC_SC_REG_MTE_UB_RD_OVFLW_MASK_LEN              1
#define AIC_SC_REG_MTE_UB_RD_OVFLW_MASK_OFFSET           29
#define AIC_SC_REG_MTE_UB_WR_OVFLW_MASK_LEN              1
#define AIC_SC_REG_MTE_UB_WR_OVFLW_MASK_OFFSET           28
#define AIC_SC_REG_CCU_PB_ECC_ERR_MASK_LEN               1
#define AIC_SC_REG_CCU_PB_ECC_ERR_MASK_OFFSET            27
#define AIC_SC_REG_CCU_LSU_ERR_MASK_LEN                  1
#define AIC_SC_REG_CCU_LSU_ERR_MASK_OFFSET               26
#define AIC_SC_REG_CCU_MPU_ERR_MASK_LEN                  1
#define AIC_SC_REG_CCU_MPU_ERR_MASK_OFFSET               25
#define AIC_SC_REG_CCU_SEQ_ERR_MASK_LEN                  1
#define AIC_SC_REG_CCU_SEQ_ERR_MASK_OFFSET               24
#define AIC_SC_REG_MTE_ERR_WAIPP_MASK_LEN                1
#define AIC_SC_REG_MTE_ERR_WAIPP_MASK_OFFSET             23
#define AIC_SC_REG_MTE_ERR_HEBCE_MASK_LEN                1
#define AIC_SC_REG_MTE_ERR_HEBCE_MASK_OFFSET             22
#define AIC_SC_REG_MTE_ERR_HEBCD_MASK_LEN                1
#define AIC_SC_REG_MTE_ERR_HEBCD_MASK_OFFSET             21
#define AIC_SC_REG_MTE_ERR_INSTR_ILLEGAL_CFG_MASK_LEN    1
#define AIC_SC_REG_MTE_ERR_INSTR_ILLEGAL_CFG_MASK_OFFSET 20
#define AIC_SC_REG_CUBE_ERR_HSET_CNT_OVF_MASK_LEN        1
#define AIC_SC_REG_CUBE_ERR_HSET_CNT_OVF_MASK_OFFSET     19
#define AIC_SC_REG_CUBE_ERR_HSET_CNT_UNF_MASK_LEN        1
#define AIC_SC_REG_CUBE_ERR_HSET_CNT_UNF_MASK_OFFSET     18
#define AIC_SC_REG_MTE_ERR_CACHE_ECC_MASK_LEN            1
#define AIC_SC_REG_MTE_ERR_CACHE_ECC_MASK_OFFSET         17
#define AIC_SC_REG_CCU_ERR_PARITY_ERR_MASK_LEN           1
#define AIC_SC_REG_CCU_ERR_PARITY_ERR_MASK_OFFSET        16
#define AIC_SC_REG_MTE_ERR_WAITSET_MASK_LEN              1
#define AIC_SC_REG_MTE_ERR_WAITSET_MASK_OFFSET           15
#define AIC_SC_REG_MTE_ERR_FIFO_PARITY_MASK_LEN          1
#define AIC_SC_REG_MTE_ERR_FIFO_PARITY_MASK_OFFSET       14
#define AIC_SC_REG_SC_REG_PARITY_ERR_MASK_LEN            1
#define AIC_SC_REG_SC_REG_PARITY_ERR_MASK_OFFSET         13
#define AIC_SC_REG_FIXP_ERR_FBUF_READ_OVFLW_MASK_LEN     1
#define AIC_SC_REG_FIXP_ERR_FBUF_READ_OVFLW_MASK_OFFSET  12
#define AIC_SC_REG_FIXP_ERR_FBUF_WRITE_OVFLW_MASK_LEN    1
#define AIC_SC_REG_FIXP_ERR_FBUF_WRITE_OVFLW_MASK_OFFSET 11
#define AIC_SC_REG_FIXP_ERR_WRITE_UB_OVFLW_MASK_LEN      1
#define AIC_SC_REG_FIXP_ERR_WRITE_UB_OVFLW_MASK_OFFSET   10
#define AIC_SC_REG_FIXP_ERR_WRITE_L1_OVFLW_MASK_LEN      1
#define AIC_SC_REG_FIXP_ERR_WRITE_L1_OVFLW_MASK_OFFSET   9
#define AIC_SC_REG_FIXP_ERR_READ_UB_OVFLW_MASK_LEN       1
#define AIC_SC_REG_FIXP_ERR_READ_UB_OVFLW_MASK_OFFSET    8
#define AIC_SC_REG_FIXP_ERR_READ_L1_OVFLW_MASK_LEN       1
#define AIC_SC_REG_FIXP_ERR_READ_L1_OVFLW_MASK_OFFSET    7
#define AIC_SC_REG_FIXP_ERR_READ_L0C_OVFLW_MASK_LEN      1
#define AIC_SC_REG_FIXP_ERR_READ_L0C_OVFLW_MASK_OFFSET   6
#define AIC_SC_REG_FIXP_ERR_ILLEGAL_CFG_MASK_LEN         1
#define AIC_SC_REG_FIXP_ERR_ILLEGAL_CFG_MASK_OFFSET      5
#define AIC_SC_REG_FIXP_ERR_INSTR_ADDR_MISAL_MASK_LEN    1
#define AIC_SC_REG_FIXP_ERR_INSTR_ADDR_MISAL_MASK_OFFSET 4
#define AIC_SC_REG_CNT_SW_BUS_ERR_MASK_LEN               1
#define AIC_SC_REG_CNT_SW_BUS_ERR_MASK_OFFSET            3
#define AIC_SC_REG_CCU_NEG_SQRT_FP_MASK_LEN              1
#define AIC_SC_REG_CCU_NEG_SQRT_FP_MASK_OFFSET           2
#define AIC_SC_REG_CCU_DIV0_FP_MASK_LEN                  1
#define AIC_SC_REG_CCU_DIV0_FP_MASK_OFFSET               1
#define AIC_SC_REG_CCU_DC_TAG_ECC_MASK_LEN               1
#define AIC_SC_REG_CCU_DC_TAG_ECC_MASK_OFFSET            0

#define AIC_SC_REG_CCU_BUS_ERR_ADDR_0_LEN    32
#define AIC_SC_REG_CCU_BUS_ERR_ADDR_0_OFFSET 0

#define AIC_SC_REG_CCU_BUS_ERR_TYPE_LEN      4
#define AIC_SC_REG_CCU_BUS_ERR_TYPE_OFFSET   16
#define AIC_SC_REG_CCU_BUS_ERR_ADDR_1_LEN    16
#define AIC_SC_REG_CCU_BUS_ERR_ADDR_1_OFFSET 0

#define AIC_SC_REG_SC_CNT_SW_ADDR_0_LEN    32
#define AIC_SC_REG_SC_CNT_SW_ADDR_0_OFFSET 0

#define AIC_SC_REG_SC_CNT_SW_ADDR_1_LEN    16
#define AIC_SC_REG_SC_CNT_SW_ADDR_1_OFFSET 0

#define AIC_SC_REG_MTE_ERR_L0C_RDWR_CFLT_LEN          1
#define AIC_SC_REG_MTE_ERR_L0C_RDWR_CFLT_OFFSET       16
#define AIC_SC_REG_FIXP_L0C_ECC_LEN                   1
#define AIC_SC_REG_FIXP_L0C_ECC_OFFSET                15
#define AIC_SC_REG_CUBE_ERR_PBUF_WRAP_AROUND_LEN      1
#define AIC_SC_REG_CUBE_ERR_PBUF_WRAP_AROUND_OFFSET   14
#define AIC_SC_REG_FIXP_ERR_OUT_WRITE_OVERFLOW_LEN    1
#define AIC_SC_REG_FIXP_ERR_OUT_WRITE_OVERFLOW_OFFSET 13
#define AIC_SC_REG_CCU_CROSS_CORE_SET_OVFL_ERR_LEN    1
#define AIC_SC_REG_CCU_CROSS_CORE_SET_OVFL_ERR_OFFSET 12
#define AIC_SC_REG_CCU_LSU_ATOMIC_ERR_LEN             1
#define AIC_SC_REG_CCU_LSU_ATOMIC_ERR_OFFSET          11
#define AIC_SC_REG_MTE_AIPP_ECC_ERR_LEN               1
#define AIC_SC_REG_MTE_AIPP_ECC_ERR_OFFSET            10
#define AIC_SC_REG_MTE_STB_ECC_ERR_LEN                1
#define AIC_SC_REG_MTE_STB_ECC_ERR_OFFSET             9
#define AIC_SC_REG_BIU_UNSPLIT_ERR_LEN                1
#define AIC_SC_REG_BIU_UNSPLIT_ERR_OFFSET             8
#define AIC_SC_REG_CCU_UB_OVERFLOW_ERR_LEN            1
#define AIC_SC_REG_CCU_UB_OVERFLOW_ERR_OFFSET         7
#define AIC_SC_REG_CCU_UB_WR_CFLT_LEN                 1
#define AIC_SC_REG_CCU_UB_WR_CFLT_OFFSET              6
#define AIC_SC_REG_CCU_UB_RD_CFLT_LEN                 1
#define AIC_SC_REG_CCU_UB_RD_CFLT_OFFSET              5
#define AIC_SC_REG_MTE_KTABLE_RD_ADDR_OVERFLOW_LEN    1
#define AIC_SC_REG_MTE_KTABLE_RD_ADDR_OVERFLOW_OFFSET 4
#define AIC_SC_REG_MTE_KTABLE_WR_ADDR_OVERFLOW_LEN    1
#define AIC_SC_REG_MTE_KTABLE_WR_ADDR_OVERFLOW_OFFSET 3
#define AIC_SC_REG_MTE_UB_WR_CFLT_LEN                 1
#define AIC_SC_REG_MTE_UB_WR_CFLT_OFFSET              2
#define AIC_SC_REG_MTE_UB_RD_CFLT_LEN                 1
#define AIC_SC_REG_MTE_UB_RD_CFLT_OFFSET              1
#define AIC_SC_REG_MTE_TIMEOUT_LEN                    1
#define AIC_SC_REG_MTE_TIMEOUT_OFFSET                 0

#define AIC_SC_REG_MTE_ERR_L0C_RDWR_CFLT_MASK_LEN          1
#define AIC_SC_REG_MTE_ERR_L0C_RDWR_CFLT_MASK_OFFSET       16
#define AIC_SC_REG_FIXP_L0C_ECC_MASK_LEN                   1
#define AIC_SC_REG_FIXP_L0C_ECC_MASK_OFFSET                15
#define AIC_SC_REG_CUBE_ERR_PBUF_WRAP_AROUND_MASK_LEN      1
#define AIC_SC_REG_CUBE_ERR_PBUF_WRAP_AROUND_MASK_OFFSET   14
#define AIC_SC_REG_FIXP_ERR_OUT_WRITE_OVERFLOW_MASK_LEN    1
#define AIC_SC_REG_FIXP_ERR_OUT_WRITE_OVERFLOW_MASK_OFFSET 13
#define AIC_SC_REG_CCU_CROSS_CORE_SET_OVFL_ERR_MASK_LEN    1
#define AIC_SC_REG_CCU_CROSS_CORE_SET_OVFL_ERR_MASK_OFFSET 12
#define AIC_SC_REG_CCU_LSU_ATOMIC_ERR_MASK_LEN             1
#define AIC_SC_REG_CCU_LSU_ATOMIC_ERR_MASK_OFFSET          11
#define AIC_SC_REG_MTE_AIPP_ECC_ERR_MASK_LEN               1
#define AIC_SC_REG_MTE_AIPP_ECC_ERR_MASK_OFFSET            10
#define AIC_SC_REG_MTE_STB_ECC_ERR_MASK_LEN                1
#define AIC_SC_REG_MTE_STB_ECC_ERR_MASK_OFFSET             9
#define AIC_SC_REG_BIU_UNSPLIT_ERR_MASK_LEN                1
#define AIC_SC_REG_BIU_UNSPLIT_ERR_MASK_OFFSET             8
#define AIC_SC_REG_CCU_UB_OVERFLOW_ERR_MASK_LEN            1
#define AIC_SC_REG_CCU_UB_OVERFLOW_ERR_MASK_OFFSET         7
#define AIC_SC_REG_CCU_UB_WR_CFLT_MASK_LEN                 1
#define AIC_SC_REG_CCU_UB_WR_CFLT_MASK_OFFSET              6
#define AIC_SC_REG_CCU_UB_RD_CFLT_MASK_LEN                 1
#define AIC_SC_REG_CCU_UB_RD_CFLT_MASK_OFFSET              5
#define AIC_SC_REG_MTE_KTABLE_RD_ADDR_OVERFLOW_MASK_LEN    1
#define AIC_SC_REG_MTE_KTABLE_RD_ADDR_OVERFLOW_MASK_OFFSET 4
#define AIC_SC_REG_MTE_KTABLE_WR_ADDR_OVERFLOW_MASK_LEN    1
#define AIC_SC_REG_MTE_KTABLE_WR_ADDR_OVERFLOW_MASK_OFFSET 3
#define AIC_SC_REG_MTE_UB_WR_CFLT_MASK_LEN                 1
#define AIC_SC_REG_MTE_UB_WR_CFLT_MASK_OFFSET              2
#define AIC_SC_REG_MTE_UB_RD_CFLT_MASK_LEN                 1
#define AIC_SC_REG_MTE_UB_RD_CFLT_MASK_OFFSET              1
#define AIC_SC_REG_MTE_TIMEOUT_MASK_LEN                    1
#define AIC_SC_REG_MTE_TIMEOUT_MASK_OFFSET                 0

#define AIC_SC_REG_FIXP_ERR_TYPE_LEN    4
#define AIC_SC_REG_FIXP_ERR_TYPE_OFFSET 24
#define AIC_SC_REG_FIXP_ERR_ADDR_LEN    16
#define AIC_SC_REG_FIXP_ERR_ADDR_OFFSET 8
#define AIC_SC_REG_FIXP_ERR_PC_0_LEN    8
#define AIC_SC_REG_FIXP_ERR_PC_0_OFFSET 0

#define AIC_SC_REG_VEC_ERR_PARITY_ERR_LEN         1
#define AIC_SC_REG_VEC_ERR_PARITY_ERR_OFFSET      30
#define AIC_SC_REG_VEC_VALU_ILL_ISSUE_LEN         1
#define AIC_SC_REG_VEC_VALU_ILL_ISSUE_OFFSET      29
#define AIC_SC_REG_VEC_PB_READ_NO_RESP_LEN        1
#define AIC_SC_REG_VEC_PB_READ_NO_RESP_OFFSET     28
#define AIC_SC_REG_VEC_PB_ECC_MBERR_LEN           1
#define AIC_SC_REG_VEC_PB_ECC_MBERR_OFFSET        27
#define AIC_SC_REG_VEC_BIU_RESP_ERR_LEN           1
#define AIC_SC_REG_VEC_BIU_RESP_ERR_OFFSET        26
#define AIC_SC_REG_VEC_IC_ECC_ERR_LEN             1
#define AIC_SC_REG_VEC_IC_ECC_ERR_OFFSET          25
#define AIC_SC_REG_VEC_ILL_VGA_VPD_ORDER_LEN      1
#define AIC_SC_REG_VEC_ILL_VGA_VPD_ORDER_OFFSET   24
#define AIC_SC_REG_VEC_ILL_INSTR_PADDING_LEN      1
#define AIC_SC_REG_VEC_ILL_INSTR_PADDING_OFFSET   23
#define AIC_SC_REG_VEC_ST_NUM_EXCEED_LIMIT_LEN    1
#define AIC_SC_REG_VEC_ST_NUM_EXCEED_LIMIT_OFFSET 22
#define AIC_SC_REG_VEC_LD_NUM_EXCEED_LIMIT_LEN    1
#define AIC_SC_REG_VEC_LD_NUM_EXCEED_LIMIT_OFFSET 21
#define AIC_SC_REG_VEC_EX_NUM_MISMATCH_LEN        1
#define AIC_SC_REG_VEC_EX_NUM_MISMATCH_OFFSET     20
#define AIC_SC_REG_VEC_ST_NUM_MISMATCH_LEN        1
#define AIC_SC_REG_VEC_ST_NUM_MISMATCH_OFFSET     19
#define AIC_SC_REG_VEC_LD_NUM_MISMATCH_LEN        1
#define AIC_SC_REG_VEC_LD_NUM_MISMATCH_OFFSET     18
#define AIC_SC_REG_VEC_ILL_VLOOP_SREG_LEN         1
#define AIC_SC_REG_VEC_ILL_VLOOP_SREG_OFFSET      17
#define AIC_SC_REG_VEC_ILL_VLOOP_OP_LEN           1
#define AIC_SC_REG_VEC_ILL_VLOOP_OP_OFFSET        16
#define AIC_SC_REG_VEC_VCI_IDATA_OUT_RANGE_LEN    1
#define AIC_SC_REG_VEC_VCI_IDATA_OUT_RANGE_OFFSET 15
#define AIC_SC_REG_VEC_VALU_NEG_SQRT_LEN          1
#define AIC_SC_REG_VEC_VALU_NEG_SQRT_OFFSET       14
#define AIC_SC_REG_VEC_VALU_NEG_LN_LEN            1
#define AIC_SC_REG_VEC_VALU_NEG_LN_OFFSET         13
#define AIC_SC_REG_VEC_DIV_BY_ZERO_LEN            1
#define AIC_SC_REG_VEC_DIV_BY_ZERO_OFFSET         12
#define AIC_SC_REG_VEC_IDATA_INF_NAN_LEN          1
#define AIC_SC_REG_VEC_IDATA_INF_NAN_OFFSET       11
#define AIC_SC_REG_VEC_UB_ECC_MBERR_LEN           1
#define AIC_SC_REG_VEC_UB_ECC_MBERR_OFFSET        10
#define AIC_SC_REG_VEC_UB_ADDR_WRAP_AROUND_LEN    1
#define AIC_SC_REG_VEC_UB_ADDR_WRAP_AROUND_OFFSET 9
#define AIC_SC_REG_VEC_INSTR_ILL_SQZN_LEN         1
#define AIC_SC_REG_VEC_INSTR_ILL_SQZN_OFFSET      8
#define AIC_SC_REG_VEC_INSTR_ILL_MASK_LEN         1
#define AIC_SC_REG_VEC_INSTR_ILL_MASK_OFFSET      7
#define AIC_SC_REG_VEC_INSTR_MISALIGN_LEN         1
#define AIC_SC_REG_VEC_INSTR_MISALIGN_OFFSET      6
#define AIC_SC_REG_VEC_INSTR_ILL_CFG_LEN          1
#define AIC_SC_REG_VEC_INSTR_ILL_CFG_OFFSET       5
#define AIC_SC_REG_VEC_INSTRS_UNDEF_LEN           1
#define AIC_SC_REG_VEC_INSTRS_UNDEF_OFFSET        4
#define AIC_SC_REG_VEC_INSTR_TIMEOUT_LEN          1
#define AIC_SC_REG_VEC_INSTR_TIMEOUT_OFFSET       3
#define AIC_SC_REG_VEC_DATA_EXCPT_VEC_LEN         1
#define AIC_SC_REG_VEC_DATA_EXCPT_VEC_OFFSET      2
#define AIC_SC_REG_VEC_DATA_EXCPT_SU_LEN          1
#define AIC_SC_REG_VEC_DATA_EXCPT_SU_OFFSET       1
#define AIC_SC_REG_VEC_DATA_EXCPT_MTE_LEN         1
#define AIC_SC_REG_VEC_DATA_EXCPT_MTE_OFFSET      0

#define AIC_SC_REG_VEC_ERR_PARITY_ERR_MASK_LEN         1
#define AIC_SC_REG_VEC_ERR_PARITY_ERR_MASK_OFFSET      30
#define AIC_SC_REG_VEC_VALU_ILL_ISSUE_MASK_LEN         1
#define AIC_SC_REG_VEC_VALU_ILL_ISSUE_MASK_OFFSET      29
#define AIC_SC_REG_VEC_PB_READ_NO_RESP_MASK_LEN        1
#define AIC_SC_REG_VEC_PB_READ_NO_RESP_MASK_OFFSET     28
#define AIC_SC_REG_VEC_PB_ECC_MBERR_MASK_LEN           1
#define AIC_SC_REG_VEC_PB_ECC_MBERR_MASK_OFFSET        27
#define AIC_SC_REG_VEC_BIU_RESP_ERR_MASK_LEN           1
#define AIC_SC_REG_VEC_BIU_RESP_ERR_MASK_OFFSET        26
#define AIC_SC_REG_VEC_IC_ECC_ERR_MASK_LEN             1
#define AIC_SC_REG_VEC_IC_ECC_ERR_MASK_OFFSET          25
#define AIC_SC_REG_VEC_ILL_VGA_VPD_ORDER_MASK_LEN      1
#define AIC_SC_REG_VEC_ILL_VGA_VPD_ORDER_MASK_OFFSET   24
#define AIC_SC_REG_VEC_ILL_INSTR_PADDING_MASK_LEN      1
#define AIC_SC_REG_VEC_ILL_INSTR_PADDING_MASK_OFFSET   23
#define AIC_SC_REG_VEC_ST_NUM_EXCEED_LIMIT_MASK_LEN    1
#define AIC_SC_REG_VEC_ST_NUM_EXCEED_LIMIT_MASK_OFFSET 22
#define AIC_SC_REG_VEC_LD_NUM_EXCEED_LIMIT_MASK_LEN    1
#define AIC_SC_REG_VEC_LD_NUM_EXCEED_LIMIT_MASK_OFFSET 21
#define AIC_SC_REG_VEC_EX_NUM_MISMATCH_MASK_LEN        1
#define AIC_SC_REG_VEC_EX_NUM_MISMATCH_MASK_OFFSET     20
#define AIC_SC_REG_VEC_ST_NUM_MISMATCH_MASK_LEN        1
#define AIC_SC_REG_VEC_ST_NUM_MISMATCH_MASK_OFFSET     19
#define AIC_SC_REG_VEC_LD_NUM_MISMATCH_MASK_LEN        1
#define AIC_SC_REG_VEC_LD_NUM_MISMATCH_MASK_OFFSET     18
#define AIC_SC_REG_VEC_ILL_VLOOP_SREG_MASK_LEN         1
#define AIC_SC_REG_VEC_ILL_VLOOP_SREG_MASK_OFFSET      17
#define AIC_SC_REG_VEC_ILL_VLOOP_OP_MASK_LEN           1
#define AIC_SC_REG_VEC_ILL_VLOOP_OP_MASK_OFFSET        16
#define AIC_SC_REG_VEC_VCI_IDATA_OUT_RANGE_MASK_LEN    1
#define AIC_SC_REG_VEC_VCI_IDATA_OUT_RANGE_MASK_OFFSET 15
#define AIC_SC_REG_VEC_VALU_NEG_SQRT_MASK_LEN          1
#define AIC_SC_REG_VEC_VALU_NEG_SQRT_MASK_OFFSET       14
#define AIC_SC_REG_VEC_VALU_NEG_LN_MASK_LEN            1
#define AIC_SC_REG_VEC_VALU_NEG_LN_MASK_OFFSET         13
#define AIC_SC_REG_VEC_DIV_BY_ZERO_MASK_LEN            1
#define AIC_SC_REG_VEC_DIV_BY_ZERO_MASK_OFFSET         12
#define AIC_SC_REG_VEC_IDATA_INF_NAN_MASK_LEN          1
#define AIC_SC_REG_VEC_IDATA_INF_NAN_MASK_OFFSET       11
#define AIC_SC_REG_VEC_UB_ECC_MBERR_MASK_LEN           1
#define AIC_SC_REG_VEC_UB_ECC_MBERR_MASK_OFFSET        10
#define AIC_SC_REG_VEC_UB_ADDR_WRAP_AROUND_MASK_LEN    1
#define AIC_SC_REG_VEC_UB_ADDR_WRAP_AROUND_MASK_OFFSET 9
#define AIC_SC_REG_VEC_INSTR_ILL_SQZN_MASK_LEN         1
#define AIC_SC_REG_VEC_INSTR_ILL_SQZN_MASK_OFFSET      8
#define AIC_SC_REG_VEC_INSTR_ILL_MASK_MASK_LEN         1
#define AIC_SC_REG_VEC_INSTR_ILL_MASK_MASK_OFFSET      7
#define AIC_SC_REG_VEC_INSTR_MISALIGN_MASK_LEN         1
#define AIC_SC_REG_VEC_INSTR_MISALIGN_MASK_OFFSET      6
#define AIC_SC_REG_VEC_INSTR_ILL_CFG_MASK_LEN          1
#define AIC_SC_REG_VEC_INSTR_ILL_CFG_MASK_OFFSET       5
#define AIC_SC_REG_VEC_INSTRS_UNDEF_MASK_LEN           1
#define AIC_SC_REG_VEC_INSTRS_UNDEF_MASK_OFFSET        4
#define AIC_SC_REG_VEC_INSTR_TIMEOUT_MASK_LEN          1
#define AIC_SC_REG_VEC_INSTR_TIMEOUT_MASK_OFFSET       3
#define AIC_SC_REG_VEC_DATA_EXCPT_VEC_MASK_LEN         1
#define AIC_SC_REG_VEC_DATA_EXCPT_VEC_MASK_OFFSET      2
#define AIC_SC_REG_VEC_DATA_EXCPT_SU_MASK_LEN          1
#define AIC_SC_REG_VEC_DATA_EXCPT_SU_MASK_OFFSET       1
#define AIC_SC_REG_VEC_DATA_EXCPT_MTE_MASK_LEN         1
#define AIC_SC_REG_VEC_DATA_EXCPT_MTE_MASK_OFFSET      0

#define AIC_SC_REG_VEC_ERR_INSTR_OPCODE_RNG_LEN    6
#define AIC_SC_REG_VEC_ERR_INSTR_OPCODE_RNG_OFFSET 8
#define AIC_SC_REG_VEC_ERR_INSTR_PC_RNG_LEN        8
#define AIC_SC_REG_VEC_ERR_INSTR_PC_RNG_OFFSET     0

#define AIC_SC_REG_VEC_ERR_LPU_INSTR_PC_RNG_0_LEN    32
#define AIC_SC_REG_VEC_ERR_LPU_INSTR_PC_RNG_0_OFFSET 0

#define AIC_SC_REG_VEC_ERR_LPU_INSTR_RNG_LEN         1
#define AIC_SC_REG_VEC_ERR_LPU_INSTR_RNG_OFFSET      31
#define AIC_SC_REG_VEC_ERR_LPU_GATHER_D_RNG_LEN      1
#define AIC_SC_REG_VEC_ERR_LPU_GATHER_D_RNG_OFFSET   30
#define AIC_SC_REG_VEC_ERR_LPU_INSTR_PC_RNG_1_LEN    16
#define AIC_SC_REG_VEC_ERR_LPU_INSTR_PC_RNG_1_OFFSET 0

#define AIC_SC_REG_VEC_ERR_LPU_LOOP_I1_RNG_LEN    16
#define AIC_SC_REG_VEC_ERR_LPU_LOOP_I1_RNG_OFFSET 16
#define AIC_SC_REG_VEC_ERR_LPU_LOOP_I0_RNG_LEN    16
#define AIC_SC_REG_VEC_ERR_LPU_LOOP_I0_RNG_OFFSET 0

#define AIC_SC_REG_VEC_ERR_LPU_LOOP_I3_RNG_LEN    16
#define AIC_SC_REG_VEC_ERR_LPU_LOOP_I3_RNG_OFFSET 16
#define AIC_SC_REG_VEC_ERR_LPU_LOOP_I2_RNG_LEN    16
#define AIC_SC_REG_VEC_ERR_LPU_LOOP_I2_RNG_OFFSET 0

#define AIC_SC_REG_VEC_UB_ECC_SBERR_ADDR_RNG_LEN    19
#define AIC_SC_REG_VEC_UB_ECC_SBERR_ADDR_RNG_OFFSET 0

#define AIC_SC_REG_VEC_PB_ECC_MBERR_ADDR_RNG_LEN      10
#define AIC_SC_REG_VEC_PB_ECC_MBERR_ADDR_RNG_OFFSET   19
#define AIC_SC_REG_VEC_UB_ECC_MBERR_ADDR_RNG_0_LEN    19
#define AIC_SC_REG_VEC_UB_ECC_MBERR_ADDR_RNG_0_OFFSET 0

#define AIC_SC_REG_VEC_UB_ECC_MBERR_ADDR_RNG_1_LEN    15
#define AIC_SC_REG_VEC_UB_ECC_MBERR_ADDR_RNG_1_OFFSET 0

#define AIC_SC_REG_MTE_WARN_CACHE_ECC_1BIT_ADDR_LEN    10
#define AIC_SC_REG_MTE_WARN_CACHE_ECC_1BIT_ADDR_OFFSET 10
#define AIC_SC_REG_SU_PB_ECC_1BIT_ADDR_LEN             10
#define AIC_SC_REG_SU_PB_ECC_1BIT_ADDR_OFFSET          0

#define AIC_SC_REG_CCU_WARN_DC_DATA_ECC_1BIT_ADDR_LEN    13
#define AIC_SC_REG_CCU_WARN_DC_DATA_ECC_1BIT_ADDR_OFFSET 16
#define AIC_SC_REG_CCU_WARN_DC_TAG_ECC_1BIT_ADDR_LEN     13
#define AIC_SC_REG_CCU_WARN_DC_TAG_ECC_1BIT_ADDR_OFFSET  0

#define AIC_SC_REG_FIXP_ERR_PC_1_LEN    8
#define AIC_SC_REG_FIXP_ERR_PC_1_OFFSET 0

#define AIC_SC_REG_MTE_WARN_AIPP_ECC_1BIT_ADDR_LEN    16
#define AIC_SC_REG_MTE_WARN_AIPP_ECC_1BIT_ADDR_OFFSET 16
#define AIC_SC_REG_MTE_WARN_STB_ECC_1BIT_ADDR_LEN     16
#define AIC_SC_REG_MTE_WARN_STB_ECC_1BIT_ADDR_OFFSET  0

#define AIC_SC_REG_CUBE_WARN_L0B_ECC_1BIT_ADDR_H_LEN    9
#define AIC_SC_REG_CUBE_WARN_L0B_ECC_1BIT_ADDR_H_OFFSET 16
#define AIC_SC_REG_CUBE_WARN_L0A_ECC_1BIT_ADDR_H_LEN    9
#define AIC_SC_REG_CUBE_WARN_L0A_ECC_1BIT_ADDR_H_OFFSET 0

#define AIC_SC_REG_WARN_FIXP_CONV_ERR_MASK_LEN         1
#define AIC_SC_REG_WARN_FIXP_CONV_ERR_MASK_OFFSET      26
#define AIC_SC_REG_WARN_FIXP_NAN_INF_MASK_LEN          1
#define AIC_SC_REG_WARN_FIXP_NAN_INF_MASK_OFFSET       25
#define AIC_SC_REG_WARN_FIXP_OVFLOW_ERR_MASK_LEN       1
#define AIC_SC_REG_WARN_FIXP_OVFLOW_ERR_MASK_OFFSET    24
#define AIC_SC_REG_WARN_SU_ATOMIC_DES_NAN_MASK_LEN     1
#define AIC_SC_REG_WARN_SU_ATOMIC_DES_NAN_MASK_OFFSET  23
#define AIC_SC_REG_WARN_SU_ATOMIC_SRC_NAN_MASK_LEN     1
#define AIC_SC_REG_WARN_SU_ATOMIC_SRC_NAN_MASK_OFFSET  22
#define AIC_SC_REG_WARN_SU_ATOMIC_INF_MASK_LEN         1
#define AIC_SC_REG_WARN_SU_ATOMIC_INF_MASK_OFFSET      21
#define AIC_SC_REG_WARN_SU_ATOMIC_OVFL_MASK_LEN        1
#define AIC_SC_REG_WARN_SU_ATOMIC_OVFL_MASK_OFFSET     20
#define AIC_SC_REG_WARN_MTE_ATOMIC_DES_NAN_MASK_LEN    1
#define AIC_SC_REG_WARN_MTE_ATOMIC_DES_NAN_MASK_OFFSET 19
#define AIC_SC_REG_WARN_MTE_ATOMIC_SRC_NAN_MASK_LEN    1
#define AIC_SC_REG_WARN_MTE_ATOMIC_SRC_NAN_MASK_OFFSET 18
#define AIC_SC_REG_WARN_MTE_ATOMIC_INF_MASK_LEN        1
#define AIC_SC_REG_WARN_MTE_ATOMIC_INF_MASK_OFFSET     17
#define AIC_SC_REG_WARN_MTE_ATOMIC_OVFL_MASK_LEN       1
#define AIC_SC_REG_WARN_MTE_ATOMIC_OVFL_MASK_OFFSET    16
#define AIC_SC_REG_WARN_SCALAR_DIV0_MASK_LEN           1
#define AIC_SC_REG_WARN_SCALAR_DIV0_MASK_OFFSET        15
#define AIC_SC_REG_WARN_SCALAR_SQRT_NEG_MASK_LEN       1
#define AIC_SC_REG_WARN_SCALAR_SQRT_NEG_MASK_OFFSET    14
#define AIC_SC_REG_WARN_L0ABC_NAN_INF_MASK_LEN         1
#define AIC_SC_REG_WARN_L0ABC_NAN_INF_MASK_OFFSET      13
#define AIC_SC_REG_WARN_VEC_DIV0_ERR_MASK_LEN          1
#define AIC_SC_REG_WARN_VEC_DIV0_ERR_MASK_OFFSET       12
#define AIC_SC_REG_WARN_VEC_NAN_ERR_MASK_LEN           1
#define AIC_SC_REG_WARN_VEC_NAN_ERR_MASK_OFFSET        11
#define AIC_SC_REG_WARN_VEC_LN_NEG_MASK_LEN            1
#define AIC_SC_REG_WARN_VEC_LN_NEG_MASK_OFFSET         10
#define AIC_SC_REG_WARN_VEC_SQRT_NEG_MASK_LEN          1
#define AIC_SC_REG_WARN_VEC_SQRT_NEG_MASK_OFFSET       9
#define AIC_SC_REG_WARN_CUBE_NAN_INF_MASK_LEN          1
#define AIC_SC_REG_WARN_CUBE_NAN_INF_MASK_OFFSET       8
#define AIC_SC_REG_WARN_VEC_NAN_INF_MASK_LEN           1
#define AIC_SC_REG_WARN_VEC_NAN_INF_MASK_OFFSET        7
#define AIC_SC_REG_WARN_SCALAR_NAN_INF_MASK_LEN        1
#define AIC_SC_REG_WARN_SCALAR_NAN_INF_MASK_OFFSET     6
#define AIC_SC_REG_WARN_AIPP_F16_OVFL_MASK_LEN         1
#define AIC_SC_REG_WARN_AIPP_F16_OVFL_MASK_OFFSET      5
#define AIC_SC_REG_WARN_CUBE_ACC_OVFL_MASK_LEN         1
#define AIC_SC_REG_WARN_CUBE_ACC_OVFL_MASK_OFFSET      4
#define AIC_SC_REG_WARN_CONV_OVFL_MASK_LEN             1
#define AIC_SC_REG_WARN_CONV_OVFL_MASK_OFFSET          3
#define AIC_SC_REG_WARN_NEG_ERR_MASK_LEN               1
#define AIC_SC_REG_WARN_NEG_ERR_MASK_OFFSET            2
#define AIC_SC_REG_WARN_FP_OVFL_MASK_LEN               1
#define AIC_SC_REG_WARN_FP_OVFL_MASK_OFFSET            1
#define AIC_SC_REG_WARN_INT_OVFL_MASK_LEN              1
#define AIC_SC_REG_WARN_INT_OVFL_MASK_OFFSET           0

#define AIC_SC_REG_WARN_CUBE_ACC_UNDFL_MASK_LEN        1
#define AIC_SC_REG_WARN_CUBE_ACC_UNDFL_MASK_OFFSET     10
#define AIC_SC_REG_WARN_CONV_UNDFL_MASK_LEN            1
#define AIC_SC_REG_WARN_CONV_UNDFL_MASK_OFFSET         9
#define AIC_SC_REG_WARN_FP_UNDFL_MASK_LEN              1
#define AIC_SC_REG_WARN_FP_UNDFL_MASK_OFFSET           8
#define AIC_SC_REG_WARN_FIXP_NOP_CFG_INSTR_MASK_LEN    1
#define AIC_SC_REG_WARN_FIXP_NOP_CFG_INSTR_MASK_OFFSET 3
#define AIC_SC_REG_WARN_MTE_NOP_CFG_INSTR_MASK_LEN     1
#define AIC_SC_REG_WARN_MTE_NOP_CFG_INSTR_MASK_OFFSET  2
#define AIC_SC_REG_WARN_VEC_NOP_CFG_INSTR_MASK_LEN     1
#define AIC_SC_REG_WARN_VEC_NOP_CFG_INSTR_MASK_OFFSET  1
#define AIC_SC_REG_WARN_CUBE_NOP_CFG_INSTR_MASK_LEN    1
#define AIC_SC_REG_WARN_CUBE_NOP_CFG_INSTR_MASK_OFFSET 0

#define AIC_SC_REG_WARN_FIXP_CONV_ERR_LEN         1
#define AIC_SC_REG_WARN_FIXP_CONV_ERR_OFFSET      26
#define AIC_SC_REG_WARN_FIXP_NAN_INF_LEN          1
#define AIC_SC_REG_WARN_FIXP_NAN_INF_OFFSET       25
#define AIC_SC_REG_WARN_FIXP_OVFLOW_ERR_LEN       1
#define AIC_SC_REG_WARN_FIXP_OVFLOW_ERR_OFFSET    24
#define AIC_SC_REG_WARN_SU_ATOMIC_DES_NAN_LEN     1
#define AIC_SC_REG_WARN_SU_ATOMIC_DES_NAN_OFFSET  23
#define AIC_SC_REG_WARN_SU_ATOMIC_SRC_NAN_LEN     1
#define AIC_SC_REG_WARN_SU_ATOMIC_SRC_NAN_OFFSET  22
#define AIC_SC_REG_WARN_SU_ATOMIC_INF_LEN         1
#define AIC_SC_REG_WARN_SU_ATOMIC_INF_OFFSET      21
#define AIC_SC_REG_WARN_SU_ATOMIC_OVFL_LEN        1
#define AIC_SC_REG_WARN_SU_ATOMIC_OVFL_OFFSET     20
#define AIC_SC_REG_WARN_MTE_ATOMIC_DES_NAN_LEN    1
#define AIC_SC_REG_WARN_MTE_ATOMIC_DES_NAN_OFFSET 19
#define AIC_SC_REG_WARN_MTE_ATOMIC_SRC_NAN_LEN    1
#define AIC_SC_REG_WARN_MTE_ATOMIC_SRC_NAN_OFFSET 18
#define AIC_SC_REG_WARN_MTE_ATOMIC_INF_LEN        1
#define AIC_SC_REG_WARN_MTE_ATOMIC_INF_OFFSET     17
#define AIC_SC_REG_WARN_MTE_ATOMIC_OVFL_LEN       1
#define AIC_SC_REG_WARN_MTE_ATOMIC_OVFL_OFFSET    16
#define AIC_SC_REG_WARN_SCALAR_DIV0_LEN           1
#define AIC_SC_REG_WARN_SCALAR_DIV0_OFFSET        15
#define AIC_SC_REG_WARN_SCALAR_SQRT_NEG_LEN       1
#define AIC_SC_REG_WARN_SCALAR_SQRT_NEG_OFFSET    14
#define AIC_SC_REG_WARN_L0ABC_NAN_INF_LEN         1
#define AIC_SC_REG_WARN_L0ABC_NAN_INF_OFFSET      13
#define AIC_SC_REG_WARN_VEC_DIV0_ERR_LEN          1
#define AIC_SC_REG_WARN_VEC_DIV0_ERR_OFFSET       12
#define AIC_SC_REG_WARN_VEC_NAN_ERR_LEN           1
#define AIC_SC_REG_WARN_VEC_NAN_ERR_OFFSET        11
#define AIC_SC_REG_WARN_VEC_LN_NEG_LEN            1
#define AIC_SC_REG_WARN_VEC_LN_NEG_OFFSET         10
#define AIC_SC_REG_WARN_VEC_SQRT_NEG_LEN          1
#define AIC_SC_REG_WARN_VEC_SQRT_NEG_OFFSET       9
#define AIC_SC_REG_WARN_CUBE_NAN_INF_LEN          1
#define AIC_SC_REG_WARN_CUBE_NAN_INF_OFFSET       8
#define AIC_SC_REG_WARN_VEC_NAN_INF_LEN           1
#define AIC_SC_REG_WARN_VEC_NAN_INF_OFFSET        7
#define AIC_SC_REG_WARN_SCALAR_NAN_INF_LEN        1
#define AIC_SC_REG_WARN_SCALAR_NAN_INF_OFFSET     6
#define AIC_SC_REG_WARN_AIPP_F16_OVFL_LEN         1
#define AIC_SC_REG_WARN_AIPP_F16_OVFL_OFFSET      5
#define AIC_SC_REG_WARN_CUBE_ACC_OVFL_LEN         1
#define AIC_SC_REG_WARN_CUBE_ACC_OVFL_OFFSET      4
#define AIC_SC_REG_WARN_CONV_OVFL_LEN             1
#define AIC_SC_REG_WARN_CONV_OVFL_OFFSET          3
#define AIC_SC_REG_WARN_NEG_ERR_LEN               1
#define AIC_SC_REG_WARN_NEG_ERR_OFFSET            2
#define AIC_SC_REG_WARN_FP_OVFL_LEN               1
#define AIC_SC_REG_WARN_FP_OVFL_OFFSET            1
#define AIC_SC_REG_WARN_INT_OVFL_LEN              1
#define AIC_SC_REG_WARN_INT_OVFL_OFFSET           0

#define AIC_SC_REG_WARN_CUBE_ACC_UNDFL_LEN        1
#define AIC_SC_REG_WARN_CUBE_ACC_UNDFL_OFFSET     10
#define AIC_SC_REG_WARN_CONV_UNDFL_LEN            1
#define AIC_SC_REG_WARN_CONV_UNDFL_OFFSET         9
#define AIC_SC_REG_WARN_FP_UNDFL_LEN              1
#define AIC_SC_REG_WARN_FP_UNDFL_OFFSET           8
#define AIC_SC_REG_WARN_FIXP_NOP_CFG_INSTR_LEN    1
#define AIC_SC_REG_WARN_FIXP_NOP_CFG_INSTR_OFFSET 3
#define AIC_SC_REG_WARN_MTE_NOP_CFG_INSTR_LEN     1
#define AIC_SC_REG_WARN_MTE_NOP_CFG_INSTR_OFFSET  2
#define AIC_SC_REG_WARN_VEC_NOP_CFG_INSTR_LEN     1
#define AIC_SC_REG_WARN_VEC_NOP_CFG_INSTR_OFFSET  1
#define AIC_SC_REG_WARN_CUBE_NOP_CFG_INSTR_LEN    1
#define AIC_SC_REG_WARN_CUBE_NOP_CFG_INSTR_OFFSET 0

#define AIC_SC_REG_SPR_STATUS_0_LEN    32
#define AIC_SC_REG_SPR_STATUS_0_OFFSET 0

#define AIC_SC_REG_SPR_STATUS_1_LEN    32
#define AIC_SC_REG_SPR_STATUS_1_OFFSET 0

#define AIC_SC_REG_PCT_CTRL_RESERVED_0_LEN             23
#define AIC_SC_REG_PCT_CTRL_RESERVED_0_OFFSET          9
#define AIC_SC_REG_PCT_CTRL_INSTRS_SINGLE_ISSUE_LEN    1
#define AIC_SC_REG_PCT_CTRL_INSTRS_SINGLE_ISSUE_OFFSET 8
#define AIC_SC_REG_PCT_TIMESTAMP_EN_DLY_LEN            4
#define AIC_SC_REG_PCT_TIMESTAMP_EN_DLY_OFFSET         4
#define AIC_SC_REG_PCT_TIMESTAMP_GRAY_LEN              1
#define AIC_SC_REG_PCT_TIMESTAMP_GRAY_OFFSET           3
#define AIC_SC_REG_PCT_LOOP_INSTR_EN_LEN               1
#define AIC_SC_REG_PCT_LOOP_INSTR_EN_OFFSET            2
#define AIC_SC_REG_PCT_USER_PROFILE_MODE_LEN           1
#define AIC_SC_REG_PCT_USER_PROFILE_MODE_OFFSET        1
#define AIC_SC_REG_PCT_EN_LEN                          1
#define AIC_SC_REG_PCT_EN_OFFSET                       0

#define AIC_SC_REG_PCT_CTRL_RESERVED_1_LEN    32
#define AIC_SC_REG_PCT_CTRL_RESERVED_1_OFFSET 0

#define AIC_SC_REG_PCT_WARNING_LEN     1
#define AIC_SC_REG_PCT_WARNING_OFFSET  3
#define AIC_SC_REG_PCT_BUF_ERR_LEN     1
#define AIC_SC_REG_PCT_BUF_ERR_OFFSET  2
#define AIC_SC_REG_PCT_DONE_LEN        1
#define AIC_SC_REG_PCT_DONE_OFFSET     1
#define AIC_SC_REG_PCT_OVERFLOW_LEN    1
#define AIC_SC_REG_PCT_OVERFLOW_OFFSET 0

#define AIC_SC_REG_PCT_NUM_ENTRIES_LEN    10
#define AIC_SC_REG_PCT_NUM_ENTRIES_OFFSET 0

#define AIC_SC_REG_PCT_START_CNT_CYC_0_LEN    32
#define AIC_SC_REG_PCT_START_CNT_CYC_0_OFFSET 0

#define AIC_SC_REG_PCT_START_CNT_CYC_1_LEN    32
#define AIC_SC_REG_PCT_START_CNT_CYC_1_OFFSET 0

#define AIC_SC_REG_PCT_STOP_CNT_CYC_0_LEN    32
#define AIC_SC_REG_PCT_STOP_CNT_CYC_0_OFFSET 0

#define AIC_SC_REG_PCT_STOP_CNT_CYC_1_LEN    32
#define AIC_SC_REG_PCT_STOP_CNT_CYC_1_OFFSET 0

#define AIC_SC_REG_PCT_OV_TIMESTAMP_0_LEN    32
#define AIC_SC_REG_PCT_OV_TIMESTAMP_0_OFFSET 0

#define AIC_SC_REG_PCT_OV_TIMESTAMP_1_LEN    32
#define AIC_SC_REG_PCT_OV_TIMESTAMP_1_OFFSET 0

#define AIC_SC_REG_VEC_EX_IDLE_WARM_UP_EN_LEN      1
#define AIC_SC_REG_VEC_EX_IDLE_WARM_UP_EN_OFFSET   26
#define AIC_SC_REG_VEC_LDST_WARM_UP_EN_LEN         1
#define AIC_SC_REG_VEC_LDST_WARM_UP_EN_OFFSET      25
#define AIC_SC_REG_VEC_IFU_IDLE_MODE_LEN           1
#define AIC_SC_REG_VEC_IFU_IDLE_MODE_OFFSET        24
#define AIC_SC_REG_VEC_ERR_DISAB_LEN               1
#define AIC_SC_REG_VEC_ERR_DISAB_OFFSET            23
#define AIC_SC_REG_VEC_PEEK_ENTRY_DISAB_LEN        1
#define AIC_SC_REG_VEC_PEEK_ENTRY_DISAB_OFFSET     22
#define AIC_SC_REG_VEC_FAST_CSW_PID_LEN            1
#define AIC_SC_REG_VEC_FAST_CSW_PID_OFFSET         21
#define AIC_SC_REG_VEC_WARM_UP_LANE_NUM_LEN        5
#define AIC_SC_REG_VEC_WARM_UP_LANE_NUM_OFFSET     16
#define AIC_SC_REG_VEC_WARM_UP_RAMP_CYC_LEN        8
#define AIC_SC_REG_VEC_WARM_UP_RAMP_CYC_OFFSET     8
#define AIC_SC_REG_VEC_WARM_UP_EN_LEN              1
#define AIC_SC_REG_VEC_WARM_UP_EN_OFFSET           7
#define AIC_SC_REG_VEC_FAST_CSW_MASK_LEN           1
#define AIC_SC_REG_VEC_FAST_CSW_MASK_OFFSET        6
#define AIC_SC_REG_VEC_UB_RANDOM_RD_EN_LEN         1
#define AIC_SC_REG_VEC_UB_RANDOM_RD_EN_OFFSET      5
#define AIC_SC_REG_VEC_GLB_ACTIVE_EN_LEN           1
#define AIC_SC_REG_VEC_GLB_ACTIVE_EN_OFFSET        4
#define AIC_SC_REG_VEC_INSTR_FUSION_DISABLE_LEN    1
#define AIC_SC_REG_VEC_INSTR_FUSION_DISABLE_OFFSET 3
#define AIC_SC_REG_VEC_COL2IMG_CFLT_CHK_EN_LEN     1
#define AIC_SC_REG_VEC_COL2IMG_CFLT_CHK_EN_OFFSET  2
#define AIC_SC_REG_VEC_VMS4_CHICKEN_EN_LEN         1
#define AIC_SC_REG_VEC_VMS4_CHICKEN_EN_OFFSET      1
#define AIC_SC_REG_VEC_WB_MRG_DISABLE_LEN          1
#define AIC_SC_REG_VEC_WB_MRG_DISABLE_OFFSET       0

#define AIC_SC_REG_VEC_FINAL_WARM_UP_CYC_LEN    8
#define AIC_SC_REG_VEC_FINAL_WARM_UP_CYC_OFFSET 24
#define AIC_SC_REG_VEC_IDLE_GUARD_CYC_LEN       8
#define AIC_SC_REG_VEC_IDLE_GUARD_CYC_OFFSET    16
#define AIC_SC_REG_VEC_DUMMY_DATA1_LEN          8
#define AIC_SC_REG_VEC_DUMMY_DATA1_OFFSET       8
#define AIC_SC_REG_VEC_DUMMY_DATA0_LEN          8
#define AIC_SC_REG_VEC_DUMMY_DATA0_OFFSET       0

#define AIC_SC_REG_VEC_RUNTIME_THR_LEN    20
#define AIC_SC_REG_VEC_RUNTIME_THR_OFFSET 0

#define AIC_SC_REG_VEC_CLR_VLD_LEN                  1
#define AIC_SC_REG_VEC_CLR_VLD_OFFSET               31
#define AIC_SC_REG_VEC_SINGLE_COMMIT_MODE_EN_LEN    1
#define AIC_SC_REG_VEC_SINGLE_COMMIT_MODE_EN_OFFSET 0

#define AIC_SC_REG_VEC_CLEAR_DONE_LEN    1
#define AIC_SC_REG_VEC_CLEAR_DONE_OFFSET 2
#define AIC_SC_REG_VEC_DBG_RDY_LEN       1
#define AIC_SC_REG_VEC_DBG_RDY_OFFSET    1
#define AIC_SC_REG_VEC_DBG_DONE_LEN      1
#define AIC_SC_REG_VEC_DBG_DONE_OFFSET   0

#define AIC_SC_REG_VEC_ACTIVE_INTERVAL_CYCLE_LEN    5
#define AIC_SC_REG_VEC_ACTIVE_INTERVAL_CYCLE_OFFSET 4
#define AIC_SC_REG_VEC_ACTIVE_CFG_EN_LEN            1
#define AIC_SC_REG_VEC_ACTIVE_CFG_EN_OFFSET         1
#define AIC_SC_REG_VEC_IRDROP_DISABLE_LEN           1
#define AIC_SC_REG_VEC_IRDROP_DISABLE_OFFSET        0

#define AIC_SC_REG_VEC_RESERVED_REG00_0_LEN    32
#define AIC_SC_REG_VEC_RESERVED_REG00_0_OFFSET 0

#define AIC_SC_REG_VEC_RESERVED_REG00_1_LEN    32
#define AIC_SC_REG_VEC_RESERVED_REG00_1_OFFSET 0

#define AIC_SC_REG_VEC_RESERVED_REG01_0_LEN    32
#define AIC_SC_REG_VEC_RESERVED_REG01_0_OFFSET 0

#define AIC_SC_REG_VEC_RESERVED_REG01_1_LEN    32
#define AIC_SC_REG_VEC_RESERVED_REG01_1_OFFSET 0

#define AIC_SC_REG_CUBE_RESERVED_REG00_0_LEN    32
#define AIC_SC_REG_CUBE_RESERVED_REG00_0_OFFSET 0

#define AIC_SC_REG_CUBE_RESERVED_REG00_1_LEN    32
#define AIC_SC_REG_CUBE_RESERVED_REG00_1_OFFSET 0

#define AIC_SC_REG_CUBE_RESERVED_REG01_0_LEN    32
#define AIC_SC_REG_CUBE_RESERVED_REG01_0_OFFSET 0

#define AIC_SC_REG_CUBE_RESERVED_REG01_1_LEN    32
#define AIC_SC_REG_CUBE_RESERVED_REG01_1_OFFSET 0

#define AIC_SC_REG_SC_RESERVED_REG00_0_LEN       24
#define AIC_SC_REG_SC_RESERVED_REG00_0_OFFSET    8
#define AIC_SC_REG_SC_RESERVED_REG00_7TO4_LEN    4
#define AIC_SC_REG_SC_RESERVED_REG00_7TO4_OFFSET 4
#define AIC_SC_REG_ECO_VER_LEN                   4
#define AIC_SC_REG_ECO_VER_OFFSET                0

#define AIC_SC_REG_SC_RESERVED_REG00_1_LEN    32
#define AIC_SC_REG_SC_RESERVED_REG00_1_OFFSET 0

#define AIC_SC_REG_SC_RESERVED_REG01_31TO29_LEN     3
#define AIC_SC_REG_SC_RESERVED_REG01_31TO29_OFFSET  29
#define AIC_SC_REG_IFU_MBIST_ALL_MASK_N_LEN         1
#define AIC_SC_REG_IFU_MBIST_ALL_MASK_N_OFFSET      28
#define AIC_SC_REG_SC_RESERVED_REG01_27TO21_LEN     7
#define AIC_SC_REG_SC_RESERVED_REG01_27TO21_OFFSET  21
#define AIC_SC_REG_MTE_AIPP_MBIST_ALL_MASK_N_LEN    1
#define AIC_SC_REG_MTE_AIPP_MBIST_ALL_MASK_N_OFFSET 20
#define AIC_SC_REG_MTE_ROB_MBIST_ALL_MASK_N_LEN     4
#define AIC_SC_REG_MTE_ROB_MBIST_ALL_MASK_N_OFFSET  16
#define AIC_SC_REG_SC_RESERVED_REG01_15TO12_LEN     4
#define AIC_SC_REG_SC_RESERVED_REG01_15TO12_OFFSET  12
#define AIC_SC_REG_MTE_L0A_MBIST_ALL_MASK_N_LEN     4
#define AIC_SC_REG_MTE_L0A_MBIST_ALL_MASK_N_OFFSET  8
#define AIC_SC_REG_SC_RESERVED_REG01_7TO5_LEN       3
#define AIC_SC_REG_SC_RESERVED_REG01_7TO5_OFFSET    5
#define AIC_SC_REG_CUBE_L0B_MBIST_ALL_MASK_N_LEN    1
#define AIC_SC_REG_CUBE_L0B_MBIST_ALL_MASK_N_OFFSET 4
#define AIC_SC_REG_CUBE_L0C_MBIST_ALL_MASK_N_LEN    4
#define AIC_SC_REG_CUBE_L0C_MBIST_ALL_MASK_N_OFFSET 0

#define AIC_SC_REG_SC_RESERVED_REG01_LEN            21
#define AIC_SC_REG_SC_RESERVED_REG01_OFFSET         11
#define AIC_SC_REG_CCU_SBUF_MBIST_ALL_MASK_N_LEN    1
#define AIC_SC_REG_CCU_SBUF_MBIST_ALL_MASK_N_OFFSET 10
#define AIC_SC_REG_MTE_L1_MBIST_ALL_MASK_N_LEN      6
#define AIC_SC_REG_MTE_L1_MBIST_ALL_MASK_N_OFFSET   4
#define AIC_SC_REG_SC_RESERVED_REG01_35TO33_LEN     3
#define AIC_SC_REG_SC_RESERVED_REG01_35TO33_OFFSET  1
#define AIC_SC_REG_PCT_MBIST_ALL_MASK_N_LEN         1
#define AIC_SC_REG_PCT_MBIST_ALL_MASK_N_OFFSET      0

#define AIC_SC_REG_SC_RESERVED_RO_REG00_0_LEN    32
#define AIC_SC_REG_SC_RESERVED_RO_REG00_0_OFFSET 0

#define AIC_SC_REG_SC_RESERVED_RO_REG00_1_LEN    32
#define AIC_SC_REG_SC_RESERVED_RO_REG00_1_OFFSET 0

#define AIC_SC_REG_SC_RESERVED_RO_REG01_0_LEN    32
#define AIC_SC_REG_SC_RESERVED_RO_REG01_0_OFFSET 0

#define AIC_SC_REG_SC_RESERVED_RO_REG01_1_LEN    32
#define AIC_SC_REG_SC_RESERVED_RO_REG01_1_OFFSET 0

#define AIC_SC_REG_SC_RESERVED_REG02_0_LEN    32
#define AIC_SC_REG_SC_RESERVED_REG02_0_OFFSET 0

#define AIC_SC_REG_SC_RESERVED_REG02_1_LEN    32
#define AIC_SC_REG_SC_RESERVED_REG02_1_OFFSET 0

#define AIC_SC_REG_SC_RESERVED_REG03_0_LEN    32
#define AIC_SC_REG_SC_RESERVED_REG03_0_OFFSET 0

#define AIC_SC_REG_SC_RESERVED_REG03_1_LEN    32
#define AIC_SC_REG_SC_RESERVED_REG03_1_OFFSET 0

#define AIC_SC_REG_VEC_RESERVED_RO_REG00_0_LEN    32
#define AIC_SC_REG_VEC_RESERVED_RO_REG00_0_OFFSET 0

#define AIC_SC_REG_VEC_RESERVED_RO_REG00_1_LEN    32
#define AIC_SC_REG_VEC_RESERVED_RO_REG00_1_OFFSET 0

#define AIC_SC_REG_VEC_RESERVED_RO_REG01_0_LEN    32
#define AIC_SC_REG_VEC_RESERVED_RO_REG01_0_OFFSET 0

#define AIC_SC_REG_VEC_RESERVED_RO_REG01_1_LEN    32
#define AIC_SC_REG_VEC_RESERVED_RO_REG01_1_OFFSET 0

#define AIC_SC_REG_CUBE_RESERVED_RO_REG00_0_LEN    32
#define AIC_SC_REG_CUBE_RESERVED_RO_REG00_0_OFFSET 0

#define AIC_SC_REG_CUBE_RESERVED_RO_REG00_1_LEN    32
#define AIC_SC_REG_CUBE_RESERVED_RO_REG00_1_OFFSET 0

#define AIC_SC_REG_CUBE_RESERVED_RO_REG01_0_LEN    32
#define AIC_SC_REG_CUBE_RESERVED_RO_REG01_0_OFFSET 0

#define AIC_SC_REG_CUBE_RESERVED_RO_REG01_1_LEN    32
#define AIC_SC_REG_CUBE_RESERVED_RO_REG01_1_OFFSET 0

#define AIC_SC_REG_BRIF_CFG_LEN             8
#define AIC_SC_REG_BRIF_CFG_OFFSET          24
#define AIC_SC_REG_BWIF_CFG_LEN             8
#define AIC_SC_REG_BWIF_CFG_OFFSET          16
#define AIC_SC_REG_MTE_MVF_CACHE_CTL_LEN    2
#define AIC_SC_REG_MTE_MVF_CACHE_CTL_OFFSET 1
#define AIC_SC_REG_MTE_FUSE_EN_LEN          1
#define AIC_SC_REG_MTE_FUSE_EN_OFFSET       0

#define AIC_SC_REG_MTE_SID_HW_REMAP_EN_LEN    1
#define AIC_SC_REG_MTE_SID_HW_REMAP_EN_OFFSET 31
#define AIC_SC_REG_MTE_ATM_RLAST_CFG_LEN      2
#define AIC_SC_REG_MTE_ATM_RLAST_CFG_OFFSET   28
#define AIC_SC_REG_MTE_UB_WR_COMB_EN_LEN      1
#define AIC_SC_REG_MTE_UB_WR_COMB_EN_OFFSET   21
#define AIC_SC_REG_MTE_AIPP_RSV_0_LEN         16
#define AIC_SC_REG_MTE_AIPP_RSV_0_OFFSET      5
#define AIC_SC_REG_MTE_L1_WR_ARB_CFG_LEN      4
#define AIC_SC_REG_MTE_L1_WR_ARB_CFG_OFFSET   1
#define AIC_SC_REG_MTE_ERLY_PTH_EN_N_LEN      1
#define AIC_SC_REG_MTE_ERLY_PTH_EN_N_OFFSET   0

#define AIC_SC_REG_MTE_WRMUP_CYC_CNT_LEN       8
#define AIC_SC_REG_MTE_WRMUP_CYC_CNT_OFFSET    16
#define AIC_SC_REG_MTE_WRMUP_BK_NUM_LEN        5
#define AIC_SC_REG_MTE_WRMUP_BK_NUM_OFFSET     8
#define AIC_SC_REG_MTE_WRMUP_BK_NUM_MAX_LEN    5
#define AIC_SC_REG_MTE_WRMUP_BK_NUM_MAX_OFFSET 0

#define AIC_SC_REG_MTE_WRMUP_GL_EN_LEN     1
#define AIC_SC_REG_MTE_WRMUP_GL_EN_OFFSET  16
#define AIC_SC_REG_MTE_WRMUP_GT_CNT_LEN    16
#define AIC_SC_REG_MTE_WRMUP_GT_CNT_OFFSET 0

#define AIC_SC_REG_MTE_AIPP_RSV_1_LEN    16
#define AIC_SC_REG_MTE_AIPP_RSV_1_OFFSET 0







#define AIC_SC_REG_MTE_FIXP_RSV_LEN    15
#define AIC_SC_REG_MTE_FIXP_RSV_OFFSET 0

#define AIC_SC_REG_FIXP_WRMUP_EN_LEN      1
#define AIC_SC_REG_FIXP_WRMUP_EN_OFFSET   31
#define AIC_SC_REG_FIXP_WRMUP_DATA_LEN    16
#define AIC_SC_REG_FIXP_WRMUP_DATA_OFFSET 0

#define AIC_SC_REG_FIXP_WRMUP_LANE_CNT_LEN    8
#define AIC_SC_REG_FIXP_WRMUP_LANE_CNT_OFFSET 16
#define AIC_SC_REG_FIXP_WRMUP_GT_CNT_LEN      16
#define AIC_SC_REG_FIXP_WRMUP_GT_CNT_OFFSET   0

#define AIC_SC_REG_FIXP_INSTR_FUSE_DISABLE_LEN    1
#define AIC_SC_REG_FIXP_INSTR_FUSE_DISABLE_OFFSET 0

#define AIC_SC_REG_MTE_TASK_END_CFG_LEN    8
#define AIC_SC_REG_MTE_TASK_END_CFG_OFFSET 0

#define AIC_SC_REG_MTE_PCIE_TYPE_BURST_LEN_LEN    2
#define AIC_SC_REG_MTE_PCIE_TYPE_BURST_LEN_OFFSET 0

#define AIC_SC_REG_MTE_PCIE_WIN_SIZE_LEN    5
#define AIC_SC_REG_MTE_PCIE_WIN_SIZE_OFFSET 0

#define AIC_SC_REG_MTE_PCIE_WIN_BASE_LEN    18
#define AIC_SC_REG_MTE_PCIE_WIN_BASE_OFFSET 0

#define AIC_SC_REG_MTE_PCIE_EN_LEN    1
#define AIC_SC_REG_MTE_PCIE_EN_OFFSET 0

#define AIC_SC_REG_CUBE_ACTIVE_INTERVAL_CYCLE_0_LEN    4
#define AIC_SC_REG_CUBE_ACTIVE_INTERVAL_CYCLE_0_OFFSET 28
#define AIC_SC_REG_CUBE_ACTIVE_CFG_EN_LEN              1
#define AIC_SC_REG_CUBE_ACTIVE_CFG_EN_OFFSET           27
#define AIC_SC_REG_CUBE_INST_INTERVAL_CYCLE_LEN        6
#define AIC_SC_REG_CUBE_INST_INTERVAL_CYCLE_OFFSET     21
#define AIC_SC_REG_CUBE_VDROP_EN_LEN                   1
#define AIC_SC_REG_CUBE_VDROP_EN_OFFSET                20
#define AIC_SC_REG_CUBE_VDROP_CYCLE_LEN                6
#define AIC_SC_REG_CUBE_VDROP_CYCLE_OFFSET             14
#define AIC_SC_REG_CUBE_DUMMY_CFG_K_LEN                5
#define AIC_SC_REG_CUBE_DUMMY_CFG_K_OFFSET             9
#define AIC_SC_REG_CUBE_DUMMY_CFG_CYCLE_LEN            4
#define AIC_SC_REG_CUBE_DUMMY_CFG_CYCLE_OFFSET         5
#define AIC_SC_REG_CUBE_DUMMY_START_EN_LEN             1
#define AIC_SC_REG_CUBE_DUMMY_START_EN_OFFSET          4
#define AIC_SC_REG_CUBE_DUMMY_NOP_CYCLE_LEN            3
#define AIC_SC_REG_CUBE_DUMMY_NOP_CYCLE_OFFSET         1
#define AIC_SC_REG_CUBE_DUMMY_NOP_EN_LEN               1
#define AIC_SC_REG_CUBE_DUMMY_NOP_EN_OFFSET            0

#define AIC_SC_REG_CUBE_END_DUMMY_EN_LEN               1
#define AIC_SC_REG_CUBE_END_DUMMY_EN_OFFSET            31
#define AIC_SC_REG_CUBE_INACTIVE_CFG_EN_LEN            1
#define AIC_SC_REG_CUBE_INACTIVE_CFG_EN_OFFSET         28
#define AIC_SC_REG_CUBE_N2_MODE_LEN                    1
#define AIC_SC_REG_CUBE_N2_MODE_OFFSET                 27
#define AIC_SC_REG_CUBE_FLAG_CLR_LEN                   1
#define AIC_SC_REG_CUBE_FLAG_CLR_OFFSET                26
#define AIC_SC_REG_CUBE_DUMMY_CFG_CYCLE_1_LEN          2
#define AIC_SC_REG_CUBE_DUMMY_CFG_CYCLE_1_OFFSET       24
#define AIC_SC_REG_CUBE_DUMMY_DATA1_LEN                8
#define AIC_SC_REG_CUBE_DUMMY_DATA1_OFFSET             16
#define AIC_SC_REG_CUBE_DUMMY_DATA0_LEN                8
#define AIC_SC_REG_CUBE_DUMMY_DATA0_OFFSET             8
#define AIC_SC_REG_CUBE_DUMMY_INTERVAL_CYCLE_LEN       6
#define AIC_SC_REG_CUBE_DUMMY_INTERVAL_CYCLE_OFFSET    2
#define AIC_SC_REG_CUBE_ACTIVE_INTERVAL_CYCLE_1_LEN    2
#define AIC_SC_REG_CUBE_ACTIVE_INTERVAL_CYCLE_1_OFFSET 0

#define AIC_SC_REG_CUBE_DUMMY_CFG_MAX_K_NM_LEN        5
#define AIC_SC_REG_CUBE_DUMMY_CFG_MAX_K_NM_OFFSET     26
#define AIC_SC_REG_CUBE_DUMMY_CFG_MAX_K_WO_LEN        5
#define AIC_SC_REG_CUBE_DUMMY_CFG_MAX_K_WO_OFFSET     21
#define AIC_SC_REG_CUBE_DUMMY_CFG_MAX_K_DW_LEN        5
#define AIC_SC_REG_CUBE_DUMMY_CFG_MAX_K_DW_OFFSET     16
#define AIC_SC_REG_CUBE_DUMMY_CFG_K_STEP_LEN          5
#define AIC_SC_REG_CUBE_DUMMY_CFG_K_STEP_OFFSET       11
#define AIC_SC_REG_CUBE_DUMMY_CFG_MAX_K_LEN           5
#define AIC_SC_REG_CUBE_DUMMY_CFG_MAX_K_OFFSET        6
#define AIC_SC_REG_CUBE_DUMMY_CFG_K_STEP_CYCLE_LEN    6
#define AIC_SC_REG_CUBE_DUMMY_CFG_K_STEP_CYCLE_OFFSET 0

#define AIC_SC_REG_CUBE_HSET_HWAIT_RESET_LEN            1
#define AIC_SC_REG_CUBE_HSET_HWAIT_RESET_OFFSET         31
#define AIC_SC_REG_CUBE_DUMMY_CFG_MAX_K_SP_LEN          5
#define AIC_SC_REG_CUBE_DUMMY_CFG_MAX_K_SP_OFFSET       12
#define AIC_SC_REG_CUBE_STALL_DUMMY_CFG_LEN             4
#define AIC_SC_REG_CUBE_STALL_DUMMY_CFG_OFFSET          8
#define AIC_SC_REG_CUBE_HSET_HWAIT_COUNTER_RANGE_LEN    6
#define AIC_SC_REG_CUBE_HSET_HWAIT_COUNTER_RANGE_OFFSET 0

#define AIC_SC_REG_BIU8_STATUS2_0_LEN    32
#define AIC_SC_REG_BIU8_STATUS2_0_OFFSET 0

#define AIC_SC_REG_BIU8_STATUS2_1_LEN    32
#define AIC_SC_REG_BIU8_STATUS2_1_OFFSET 0

#define AIC_SC_REG_BIU8_STATUS3_0_LEN    32
#define AIC_SC_REG_BIU8_STATUS3_0_OFFSET 0

#define AIC_SC_REG_BIU8_STATUS3_1_LEN    32
#define AIC_SC_REG_BIU8_STATUS3_1_OFFSET 0

#define AIC_SC_REG_BIU8_STATUS4_0_LEN    32
#define AIC_SC_REG_BIU8_STATUS4_0_OFFSET 0

#define AIC_SC_REG_BIU8_STATUS4_1_LEN    32
#define AIC_SC_REG_BIU8_STATUS4_1_OFFSET 0

#define AIC_SC_REG_BIU8_SMMU_STREAMID_LEN    16
#define AIC_SC_REG_BIU8_SMMU_STREAMID_OFFSET 0

#define AIC_SC_REG_BIU8_L2_PADDR_BASE_0_LEN    32
#define AIC_SC_REG_BIU8_L2_PADDR_BASE_0_OFFSET 0

#define AIC_SC_REG_BIU8_L2_PADDR_BASE_1_LEN    32
#define AIC_SC_REG_BIU8_L2_PADDR_BASE_1_OFFSET 0

#define AIC_SC_REG_BIU8_L2_PAGE_SIZE_LEN    3
#define AIC_SC_REG_BIU8_L2_PAGE_SIZE_OFFSET 0

#define AIC_SC_REG_BIU8_L2_SIZE_LEN    3
#define AIC_SC_REG_BIU8_L2_SIZE_OFFSET 0

#define AIC_SC_REG_BIU8_L2_REMAP_EN_LEN    1
#define AIC_SC_REG_BIU8_L2_REMAP_EN_OFFSET 31

#define AIC_SC_REG_BIU8_CTRL3_0_LEN    32
#define AIC_SC_REG_BIU8_CTRL3_0_OFFSET 0

#define AIC_SC_REG_BIU8_CTRL3_1_LEN    32
#define AIC_SC_REG_BIU8_CTRL3_1_OFFSET 0

#define AIC_SC_REG_BIU8_CTRL4_0_LEN    32
#define AIC_SC_REG_BIU8_CTRL4_0_OFFSET 0

#define AIC_SC_REG_BIU8_CTRL4_1_LEN    32
#define AIC_SC_REG_BIU8_CTRL4_1_OFFSET 0

#define AIC_SC_REG_BIU8_CTRL5_0_LEN    32
#define AIC_SC_REG_BIU8_CTRL5_0_OFFSET 0

#define AIC_SC_REG_BIU8_CTRL5_1_LEN    32
#define AIC_SC_REG_BIU8_CTRL5_1_OFFSET 0

#define AIC_SC_REG_BIU8_STATUS6_0_LEN    32
#define AIC_SC_REG_BIU8_STATUS6_0_OFFSET 0

#define AIC_SC_REG_BIU8_STATUS6_1_LEN    32
#define AIC_SC_REG_BIU8_STATUS6_1_OFFSET 0

#define AIC_SC_REG_BIU8_STATUS7_0_LEN    32
#define AIC_SC_REG_BIU8_STATUS7_0_OFFSET 0

#define AIC_SC_REG_BIU8_STATUS7_1_LEN    32
#define AIC_SC_REG_BIU8_STATUS7_1_OFFSET 0

#define AIC_SC_REG_TINY_EXCEPT_COMPCNT_0_LEN    32
#define AIC_SC_REG_TINY_EXCEPT_COMPCNT_0_OFFSET 0

#define AIC_SC_REG_TINY_EXCEPT_COMPCNT_BYPASS_LEN    1
#define AIC_SC_REG_TINY_EXCEPT_COMPCNT_BYPASS_OFFSET 31
#define AIC_SC_REG_TINY_EXCEPT_COMPCNT_1_LEN         31
#define AIC_SC_REG_TINY_EXCEPT_COMPCNT_1_OFFSET      0

#define AIC_SC_REG_TINY_EXCEPT_COMPCNT_INT_LEN    1
#define AIC_SC_REG_TINY_EXCEPT_COMPCNT_INT_OFFSET 0

#define AIC_SC_REG_AIC_SEC_EN_LEN    1
#define AIC_SC_REG_AIC_SEC_EN_OFFSET 0

#define AIC_SC_REG_AIC_ERR_RESP_EN_LEN    1
#define AIC_SC_REG_AIC_ERR_RESP_EN_OFFSET 0

#define AIC_SC_REG_MEM_INIT_REQ_W1_P_LEN    1
#define AIC_SC_REG_MEM_INIT_REQ_W1_P_OFFSET 0

#define AIC_SC_REG_AXI_MASTER_MASK_N_H_LEN    3
#define AIC_SC_REG_AXI_MASTER_MASK_N_H_OFFSET 27
#define AIC_SC_REG_AXI_MASTER_SRC_ID_H_LEN    3
#define AIC_SC_REG_AXI_MASTER_SRC_ID_H_OFFSET 24
#define AIC_SC_REG_AXI_MASTER_MASK_N_L_LEN    12
#define AIC_SC_REG_AXI_MASTER_MASK_N_L_OFFSET 12
#define AIC_SC_REG_AXI_MASTER_SRC_ID_L_LEN    9
#define AIC_SC_REG_AXI_MASTER_SRC_ID_L_OFFSET 3
#define AIC_SC_REG_AXI_MASTER_LP_ID_LEN       3
#define AIC_SC_REG_AXI_MASTER_LP_ID_OFFSET    0

#define AIC_SC_REG_RAM_ALWAYS_NOT_CLEAR_LEN    1
#define AIC_SC_REG_RAM_ALWAYS_NOT_CLEAR_OFFSET 0

#define AIC_SC_REG_RAM_ALWAYS_CLEAR_LEN    1
#define AIC_SC_REG_RAM_ALWAYS_CLEAR_OFFSET 0

#define AIC_SC_REG_SAFETY_INT_REG_PTY_ERR_MASK_LEN    1
#define AIC_SC_REG_SAFETY_INT_REG_PTY_ERR_MASK_OFFSET 4
#define AIC_SC_REG_SAFETY_INT_ECC_WARM_MASK_LEN       1
#define AIC_SC_REG_SAFETY_INT_ECC_WARM_MASK_OFFSET    3
#define AIC_SC_REG_SAFETY_INT_CRC_ERR_MASK_LEN        1
#define AIC_SC_REG_SAFETY_INT_CRC_ERR_MASK_OFFSET     2
#define AIC_SC_REG_SAFETY_INT_BUS_ERR_MASK_LEN        1
#define AIC_SC_REG_SAFETY_INT_BUS_ERR_MASK_OFFSET     1
#define AIC_SC_REG_SAFETY_INT_ECC_ERR_MASK_LEN        1
#define AIC_SC_REG_SAFETY_INT_ECC_ERR_MASK_OFFSET     0

#define AIC_SC_REG_SAFETY_ERR_REG_PTY_ERR_MASK_LEN    1
#define AIC_SC_REG_SAFETY_ERR_REG_PTY_ERR_MASK_OFFSET 4
#define AIC_SC_REG_SAFETY_ERR_ECC_WARM_MASK_LEN       1
#define AIC_SC_REG_SAFETY_ERR_ECC_WARM_MASK_OFFSET    3
#define AIC_SC_REG_SAFETY_ERR_CRC_ERR_MASK_LEN        1
#define AIC_SC_REG_SAFETY_ERR_CRC_ERR_MASK_OFFSET     2
#define AIC_SC_REG_SAFETY_ERR_BUS_ERR_MASK_LEN        1
#define AIC_SC_REG_SAFETY_ERR_BUS_ERR_MASK_OFFSET     1
#define AIC_SC_REG_SAFETY_ERR_ECC_ERR_MASK_LEN        1
#define AIC_SC_REG_SAFETY_ERR_ECC_ERR_MASK_OFFSET     0

#define AIC_SC_REG_SAFETY_REG_PTY_ERR_INT_LEN    1
#define AIC_SC_REG_SAFETY_REG_PTY_ERR_INT_OFFSET 4
#define AIC_SC_REG_SAFETY_ECC_WARM_INT_LEN       1
#define AIC_SC_REG_SAFETY_ECC_WARM_INT_OFFSET    3
#define AIC_SC_REG_SAFETY_CRC_ERR_INT_LEN        1
#define AIC_SC_REG_SAFETY_CRC_ERR_INT_OFFSET     2
#define AIC_SC_REG_SAFETY_BUS_ERR_INT_LEN        1
#define AIC_SC_REG_SAFETY_BUS_ERR_INT_OFFSET     1
#define AIC_SC_REG_SAFETY_ECC_ERR_INT_LEN        1
#define AIC_SC_REG_SAFETY_ECC_ERR_INT_OFFSET     0

#define AIC_SC_REG_AIC_PARITY_MASK_LEN    1
#define AIC_SC_REG_AIC_PARITY_MASK_OFFSET 1
#define AIC_SC_REG_AIC_PARITY_STOP_LEN    1
#define AIC_SC_REG_AIC_PARITY_STOP_OFFSET 0

#define AIC_SC_REG_ECC_1BIT_ERR_NUM_LEN    8
#define AIC_SC_REG_ECC_1BIT_ERR_NUM_OFFSET 0

#define AIC_SC_REG_AIC_PENDING_TASK_STA_LEN    1
#define AIC_SC_REG_AIC_PENDING_TASK_STA_OFFSET 0

#define AIC_SC_REG_AIC_PRE_RST_STALL_LEN    1
#define AIC_SC_REG_AIC_PRE_RST_STALL_OFFSET 0

#define AIC_SC_REG_AIC_PRE_RST_RDY_LEN    1
#define AIC_SC_REG_AIC_PRE_RST_RDY_OFFSET 0

#define AIC_SC_REG_AIC_EXIT_EXCPT_CLR_P_LEN    1
#define AIC_SC_REG_AIC_EXIT_EXCPT_CLR_P_OFFSET 0

#define AIC_SC_REG_DFX_MEM_WADDR_0_0_LEN    13
#define AIC_SC_REG_DFX_MEM_WADDR_0_0_OFFSET 19
#define AIC_SC_REG_DFX_MEM_WE_LEN           1
#define AIC_SC_REG_DFX_MEM_WE_OFFSET        18
#define AIC_SC_REG_DFX_MEM_ARRAY_LEN        16
#define AIC_SC_REG_DFX_MEM_ARRAY_OFFSET     2
#define AIC_SC_REG_DFX_MEM_ALL_LEN          1
#define AIC_SC_REG_DFX_MEM_ALL_OFFSET       1
#define AIC_SC_REG_DFX_MEM_REQ_LEN          1
#define AIC_SC_REG_DFX_MEM_REQ_OFFSET       0

#define AIC_SC_REG_DFX_MEM_ACCESS0_LEN      1
#define AIC_SC_REG_DFX_MEM_ACCESS0_OFFSET   31
#define AIC_SC_REG_DFX_MEM_ADD_RD_LEN       16
#define AIC_SC_REG_DFX_MEM_ADD_RD_OFFSET    12
#define AIC_SC_REG_DFX_MEM_RE_LEN           1
#define AIC_SC_REG_DFX_MEM_RE_OFFSET        8
#define AIC_SC_REG_DFX_MEM_WBE_LEN          4
#define AIC_SC_REG_DFX_MEM_WBE_OFFSET       3
#define AIC_SC_REG_DFX_MEM_WADDR_0_1_LEN    3
#define AIC_SC_REG_DFX_MEM_WADDR_0_1_OFFSET 0

#define AIC_SC_REG_DFX_MEM_RREADY_LEN      1
#define AIC_SC_REG_DFX_MEM_RREADY_OFFSET   1
#define AIC_SC_REG_DFX_MEM_WREQ_ACK_LEN    1
#define AIC_SC_REG_DFX_MEM_WREQ_ACK_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS0_WDATA0_0_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS0_WDATA0_0_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS0_WDATA0_1_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS0_WDATA0_1_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS0_WDATA1_0_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS0_WDATA1_0_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS0_WDATA1_1_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS0_WDATA1_1_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS0_WDATA2_0_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS0_WDATA2_0_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS0_WDATA2_1_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS0_WDATA2_1_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS0_WDATA3_0_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS0_WDATA3_0_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS0_WDATA3_1_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS0_WDATA3_1_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS0_WDATA4_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS0_WDATA4_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS0_RDATA0_0_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS0_RDATA0_0_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS0_RDATA0_1_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS0_RDATA0_1_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS0_RDATA1_0_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS0_RDATA1_0_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS0_RDATA1_1_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS0_RDATA1_1_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS0_RDATA2_0_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS0_RDATA2_0_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS0_RDATA2_1_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS0_RDATA2_1_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS0_RDATA3_0_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS0_RDATA3_0_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS0_RDATA3_1_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS0_RDATA3_1_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS0_RDATA4_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS0_RDATA4_OFFSET 0

#define AIC_SC_REG_DFX_MEM_WADDR1_0_LEN    13
#define AIC_SC_REG_DFX_MEM_WADDR1_0_OFFSET 19
#define AIC_SC_REG_DFX_MEM_WE1_LEN         1
#define AIC_SC_REG_DFX_MEM_WE1_OFFSET      18
#define AIC_SC_REG_DFX_MEM_ARRAY1_LEN      16
#define AIC_SC_REG_DFX_MEM_ARRAY1_OFFSET   2
#define AIC_SC_REG_DFX_MEM_ALL1_LEN        1
#define AIC_SC_REG_DFX_MEM_ALL1_OFFSET     1
#define AIC_SC_REG_DFX_MEM_REQ1_LEN        1
#define AIC_SC_REG_DFX_MEM_REQ1_OFFSET     0

#define AIC_SC_REG_DFX_MEM_ACCESS1_LEN     1
#define AIC_SC_REG_DFX_MEM_ACCESS1_OFFSET  31
#define AIC_SC_REG_DFX_MEM_ADD_RD1_LEN     16
#define AIC_SC_REG_DFX_MEM_ADD_RD1_OFFSET  5
#define AIC_SC_REG_DFX_MEM_RE1_LEN         1
#define AIC_SC_REG_DFX_MEM_RE1_OFFSET      4
#define AIC_SC_REG_DFX_MEM_WADDR1_1_LEN    3
#define AIC_SC_REG_DFX_MEM_WADDR1_1_OFFSET 0

#define AIC_SC_REG_DFX_MEM_RREADY1_LEN      1
#define AIC_SC_REG_DFX_MEM_RREADY1_OFFSET   1
#define AIC_SC_REG_DFX_MEM_WREQ_ACK1_LEN    1
#define AIC_SC_REG_DFX_MEM_WREQ_ACK1_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS1_WDATA0_0_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS1_WDATA0_0_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS1_WDATA0_1_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS1_WDATA0_1_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS1_WDATA1_0_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS1_WDATA1_0_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS1_WDATA1_1_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS1_WDATA1_1_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS1_WDATA2_0_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS1_WDATA2_0_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS1_WDATA2_1_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS1_WDATA2_1_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS1_WDATA3_0_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS1_WDATA3_0_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS1_WDATA3_1_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS1_WDATA3_1_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS1_WDATA4_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS1_WDATA4_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS1_RDATA0_0_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS1_RDATA0_0_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS1_RDATA0_1_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS1_RDATA0_1_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS1_RDATA1_0_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS1_RDATA1_0_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS1_RDATA1_1_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS1_RDATA1_1_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS1_RDATA2_0_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS1_RDATA2_0_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS1_RDATA2_1_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS1_RDATA2_1_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS1_RDATA3_0_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS1_RDATA3_0_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS1_RDATA3_1_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS1_RDATA3_1_OFFSET 0

#define AIC_SC_REG_DFX_MEM_ACCESS1_RDATA4_LEN    32
#define AIC_SC_REG_DFX_MEM_ACCESS1_RDATA4_OFFSET 0

#define AIC_SC_REG_MTE_AIPP_ECC_MB_INJECT_LEN         1
#define AIC_SC_REG_MTE_AIPP_ECC_MB_INJECT_OFFSET      31
#define AIC_SC_REG_MTE_AIPP_ECC_SB_INJECT_LEN         1
#define AIC_SC_REG_MTE_AIPP_ECC_SB_INJECT_OFFSET      30
#define AIC_SC_REG_MTE_STB_ECC_MB_INJECT_LEN          1
#define AIC_SC_REG_MTE_STB_ECC_MB_INJECT_OFFSET       29
#define AIC_SC_REG_MTE_STB_ECC_SB_INJECT_LEN          1
#define AIC_SC_REG_MTE_STB_ECC_SB_INJECT_OFFSET       28
#define AIC_SC_REG_MTE_ROB_ECC_MB_INJECT_LEN          1
#define AIC_SC_REG_MTE_ROB_ECC_MB_INJECT_OFFSET       27
#define AIC_SC_REG_MTE_ROB_ECC_SB_INJECT_LEN          1
#define AIC_SC_REG_MTE_ROB_ECC_SB_INJECT_OFFSET       26
#define AIC_SC_REG_MTE_L1_ECC_MB_INJECT_LEN           1
#define AIC_SC_REG_MTE_L1_ECC_MB_INJECT_OFFSET        25
#define AIC_SC_REG_MTE_L1_ECC_SB_INJECT_LEN           1
#define AIC_SC_REG_MTE_L1_ECC_SB_INJECT_OFFSET        24
#define AIC_SC_REG_VEC_UB_ECC_MB_INJECT_LEN           1
#define AIC_SC_REG_VEC_UB_ECC_MB_INJECT_OFFSET        17
#define AIC_SC_REG_VEC_UB_ECC_SB_INJECT_LEN           1
#define AIC_SC_REG_VEC_UB_ECC_SB_INJECT_OFFSET        16
#define AIC_SC_REG_SU_VECIQ_ECC_MB_INJECT_LEN         1
#define AIC_SC_REG_SU_VECIQ_ECC_MB_INJECT_OFFSET      14
#define AIC_SC_REG_SU_VECIQ_ECC_SB_INJECT_LEN         1
#define AIC_SC_REG_SU_VECIQ_ECC_SB_INJECT_OFFSET      13
#define AIC_SC_REG_SU_DCACHE_ECC_MB_INJECT_LEN        1
#define AIC_SC_REG_SU_DCACHE_ECC_MB_INJECT_OFFSET     12
#define AIC_SC_REG_SU_DCACHE_ECC_SB_INJECT_LEN        1
#define AIC_SC_REG_SU_DCACHE_ECC_SB_INJECT_OFFSET     11
#define AIC_SC_REG_SU_ICACHE_ECC_MB_INJECT_LEN        1
#define AIC_SC_REG_SU_ICACHE_ECC_MB_INJECT_OFFSET     10
#define AIC_SC_REG_SU_ICACHE_ECC_SB_INJECT_LEN        1
#define AIC_SC_REG_SU_ICACHE_ECC_SB_INJECT_OFFSET     9
#define AIC_SC_REG_CUBE_L0C_ECC_MB_INJECT_LEN         1
#define AIC_SC_REG_CUBE_L0C_ECC_MB_INJECT_OFFSET      7
#define AIC_SC_REG_CUBE_L0C_ECC_SB_INJECT_LEN         1
#define AIC_SC_REG_CUBE_L0C_ECC_SB_INJECT_OFFSET      6
#define AIC_SC_REG_CUBE_L0B_WINO_ECC_MB_INJECT_LEN    1
#define AIC_SC_REG_CUBE_L0B_WINO_ECC_MB_INJECT_OFFSET 5
#define AIC_SC_REG_CUBE_L0B_WINO_ECC_SB_INJECT_LEN    1
#define AIC_SC_REG_CUBE_L0B_WINO_ECC_SB_INJECT_OFFSET 4
#define AIC_SC_REG_CUBE_L0B_ECC_MB_INJECT_LEN         1
#define AIC_SC_REG_CUBE_L0B_ECC_MB_INJECT_OFFSET      3
#define AIC_SC_REG_CUBE_L0B_ECC_SB_INJECT_LEN         1
#define AIC_SC_REG_CUBE_L0B_ECC_SB_INJECT_OFFSET      2
#define AIC_SC_REG_CUBE_L0A_ECC_MB_INJECT_LEN         1
#define AIC_SC_REG_CUBE_L0A_ECC_MB_INJECT_OFFSET      1
#define AIC_SC_REG_CUBE_L0A_ECC_SB_INJECT_LEN         1
#define AIC_SC_REG_CUBE_L0A_ECC_SB_INJECT_OFFSET      0

#define AIC_SC_REG_SWITCH_BUFFER_0_LEN    30
#define AIC_SC_REG_SWITCH_BUFFER_0_OFFSET 2

#define AIC_SC_REG_CONTEXT_SWITCH_EN_LEN    1
#define AIC_SC_REG_CONTEXT_SWITCH_EN_OFFSET 31
#define AIC_SC_REG_SWITCH_BUFFER_1_LEN      16
#define AIC_SC_REG_SWITCH_BUFFER_1_OFFSET   0

#define AIC_SC_REG_SLW_CSW_BUSY_LEN                 1
#define AIC_SC_REG_SLW_CSW_BUSY_OFFSET              31
#define AIC_SC_REG_CONTEXT_SWITCH_DONE_WIDTH_LEN    4
#define AIC_SC_REG_CONTEXT_SWITCH_DONE_WIDTH_OFFSET 0

#define AIC_SC_REG_SYS_VA_BASE_0_LEN    32
#define AIC_SC_REG_SYS_VA_BASE_0_OFFSET 0

#define AIC_SC_REG_SYS_VA_BASE_1_LEN    17
#define AIC_SC_REG_SYS_VA_BASE_1_OFFSET 0

#define AIC_SC_REG_L2_VADDR_BASE_0_LEN    32
#define AIC_SC_REG_L2_VADDR_BASE_0_OFFSET 0

#define AIC_SC_REG_L2_VADDR_BASE_1_LEN    32
#define AIC_SC_REG_L2_VADDR_BASE_1_OFFSET 0

#define AIC_SC_REG_STACK_MEM_ATTRIBUTE_LEN    1
#define AIC_SC_REG_STACK_MEM_ATTRIBUTE_OFFSET 16
#define AIC_SC_REG_OUT_MEM_ATTRIBUTE_LEN      1
#define AIC_SC_REG_OUT_MEM_ATTRIBUTE_OFFSET   8
#define AIC_SC_REG_UB_MEM_ATTRIBUTE_LEN       1
#define AIC_SC_REG_UB_MEM_ATTRIBUTE_OFFSET    0

#define AIC_SC_REG_UB_BASE_OFFSET_LEN    22
#define AIC_SC_REG_UB_BASE_OFFSET_OFFSET 0

#define AIC_SC_REG_VEC_FAST_CSW_EN_LEN    1
#define AIC_SC_REG_VEC_FAST_CSW_EN_OFFSET 0

#define AIC_SC_REG_VEC_FAST_CSW_PERIOD_LEN    16
#define AIC_SC_REG_VEC_FAST_CSW_PERIOD_OFFSET 0

#define AIC_SC_REG_VEC_FAST_CSW_THR_LOW_LEN    20
#define AIC_SC_REG_VEC_FAST_CSW_THR_LOW_OFFSET 0

#define AIC_SC_REG_VEC_FAST_CSW_THR_HIGH_LEN    20
#define AIC_SC_REG_VEC_FAST_CSW_THR_HIGH_OFFSET 0

#define AIC_SC_REG_VEC_PFIFO_PEEKN_LEN    4
#define AIC_SC_REG_VEC_PFIFO_PEEKN_OFFSET 0

#define AIC_SC_REG_AIV_RESTORE_PC_0_LEN    30
#define AIC_SC_REG_AIV_RESTORE_PC_0_OFFSET 2

#define AIC_SC_REG_AIV_RESTORE_PC_1_LEN    16
#define AIC_SC_REG_AIV_RESTORE_PC_1_OFFSET 0

#define AIC_SC_REG_AIV_RESTORE_ADDR_0_LEN    30
#define AIC_SC_REG_AIV_RESTORE_ADDR_0_OFFSET 2

#define AIC_SC_REG_AIV_RESTORE_ADDR_1_LEN    16
#define AIC_SC_REG_AIV_RESTORE_ADDR_1_OFFSET 0

#define AIC_SC_REG_USE_UB_SIZE_LEN    22
#define AIC_SC_REG_USE_UB_SIZE_OFFSET 0

#define AIC_SC_REG_PMU_CNT0_IDX_LEN    12
#define AIC_SC_REG_PMU_CNT0_IDX_OFFSET 0

#define AIC_SC_REG_PMU_CNT1_IDX_LEN    12
#define AIC_SC_REG_PMU_CNT1_IDX_OFFSET 0

#define AIC_SC_REG_PMU_CNT2_IDX_LEN    12
#define AIC_SC_REG_PMU_CNT2_IDX_OFFSET 0

#define AIC_SC_REG_PMU_CNT3_IDX_LEN    12
#define AIC_SC_REG_PMU_CNT3_IDX_OFFSET 0

#define AIC_SC_REG_PMU_CNT4_IDX_LEN    12
#define AIC_SC_REG_PMU_CNT4_IDX_OFFSET 0

#define AIC_SC_REG_PMU_CNT5_IDX_LEN    12
#define AIC_SC_REG_PMU_CNT5_IDX_OFFSET 0

#define AIC_SC_REG_PMU_CNT6_IDX_LEN    12
#define AIC_SC_REG_PMU_CNT6_IDX_OFFSET 0

#define AIC_SC_REG_PMU_CNT7_IDX_LEN    12
#define AIC_SC_REG_PMU_CNT7_IDX_OFFSET 0

#define AIC_SC_REG_AIC_CROSS_CORE_BUS_PRESS_DIS_EN_LEN    1
#define AIC_SC_REG_AIC_CROSS_CORE_BUS_PRESS_DIS_EN_OFFSET 1
#define AIC_SC_REG_AIC_RUN_TASK_ONE_BY_ONE_EN_LEN         1
#define AIC_SC_REG_AIC_RUN_TASK_ONE_BY_ONE_EN_OFFSET      0

#define AIC_SC_REG_AIC_TASK_SCH_HOST_CPU_MODE_EN_LEN    1
#define AIC_SC_REG_AIC_TASK_SCH_HOST_CPU_MODE_EN_OFFSET 0

#define AIC_SC_REG_SC_REG_0X80_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0X80_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0X84_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0X84_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0X88_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0X88_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0X8C_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0X8C_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0X90_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0X90_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0X94_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0X94_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0X98_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0X98_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0X9C_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0X9C_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XA0_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XA0_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XA4_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XA4_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XA8_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XA8_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XAC_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XAC_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XB0_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XB0_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XB4_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XB4_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XB8_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XB8_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XBC_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XBC_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XC0_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XC0_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XC4_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XC4_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XC8_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XC8_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XCC_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XCC_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XD0_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XD0_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XD4_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XD4_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XD8_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XD8_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XDC_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XDC_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XE0_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XE0_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XE4_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XE4_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XE8_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XE8_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XEC_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XEC_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XF0_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XF0_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XF4_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XF4_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XF8_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XF8_BUF_OFFSET 0

#define AIC_SC_REG_SC_REG_0XFC_BUF_LEN    32
#define AIC_SC_REG_SC_REG_0XFC_BUF_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_CNT_0_0_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_CNT_0_0_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_CNT_0_1_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_CNT_0_1_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_CNT_0_2_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_CNT_0_2_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_CNT_0_3_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_CNT_0_3_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_CNT_0_4_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_CNT_0_4_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_CNT_0_5_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_CNT_0_5_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_CNT_0_6_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_CNT_0_6_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_CNT_0_7_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_CNT_0_7_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_MIN_OV_0_0_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_MIN_OV_0_0_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_MIN_OV_0_1_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_MIN_OV_0_1_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_TASK_CYC_0_0_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_TASK_CYC_0_0_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_TASK_CYC_0_1_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_TASK_CYC_0_1_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_OV_0_LEN    1
#define AIC_SC_REG_PMU_SC_FIFO_OV_0_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_CNT_1_0_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_CNT_1_0_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_CNT_1_1_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_CNT_1_1_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_CNT_1_2_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_CNT_1_2_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_CNT_1_3_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_CNT_1_3_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_CNT_1_4_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_CNT_1_4_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_CNT_1_5_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_CNT_1_5_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_CNT_1_6_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_CNT_1_6_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_CNT_1_7_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_CNT_1_7_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_MIN_OV_1_0_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_MIN_OV_1_0_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_MIN_OV_1_1_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_MIN_OV_1_1_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_TASK_CYC_1_0_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_TASK_CYC_1_0_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_TASK_CYC_1_1_LEN    32
#define AIC_SC_REG_PMU_SC_FIFO_TASK_CYC_1_1_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_OV_1_LEN    1
#define AIC_SC_REG_PMU_SC_FIFO_OV_1_OFFSET 0

#define AIC_SC_REG_PMU_SC_FIFO_WPTR_LEN    1
#define AIC_SC_REG_PMU_SC_FIFO_WPTR_OFFSET 3
#define AIC_SC_REG_PMU_SC_FIFO_RPTR_LEN    1
#define AIC_SC_REG_PMU_SC_FIFO_RPTR_OFFSET 2
#define AIC_SC_REG_PMU_SC_FIFO_NUM_LEN     2
#define AIC_SC_REG_PMU_SC_FIFO_NUM_OFFSET  0

#define AIC_SC_REG_AIC_SC_DFX_STATUS_LEN    32
#define AIC_SC_REG_AIC_SC_DFX_STATUS_OFFSET 0

#endif // __AIC_SC_REG_REG_OFFSET_FIELD_H__
